Patchwork added ich10r gpio support to intel tool

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Submitter Warren Turkal
Date 2010-08-31 01:52:11
Message ID <AANLkTinBNFvABrx95Jvp+r7aXYqYgTK6JOkea7WdUFVK@mail.gmail.com>
Download mbox | patch
Permalink /patch/1822/
State Accepted
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Comments

Warren Turkal - 2010-08-31 01:52:11
I clearly included the patch without my sign off. Here's another
exported from my git tree.

BTW, is there a git tree that is maintained and up to date? I'd rather
not use git svn if I could avoid it.

Thanks,
wt

On Mon, Aug 30, 2010 at 3:16 AM, Paul Menzel
<paulepanter@users.sourceforge.net> wrote:
> Am Montag, den 30.08.2010, 01:39 -0700 schrieb Warren Turkal:
>> I have attached a patch for ich10r support for dumping gpio registers.
>
> Thank you for your patch.
>
>> I am looking for comments and a possible committer.
>
> Please take a look at the Development Guideline and especially the
> sign-off procedure [1]. Otherwise the developers (not me) cannot commit
> your patch.
>
>
> Thanks,
>
> Paul
>
>
> [1] http://www.coreboot.org/Development_Guidelines#How_to_contribute
>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
From f9077c74a5916f42365d7d79482066e0529c029b Mon Sep 17 00:00:00 2001
From: Warren Turkal <wt@penguintechs.org>
Date: Mon, 30 Aug 2010 01:29:29 -0700
Subject: [PATCH] Add GPIOs for ICH10R southbridge.

This information comes from the Intel ICH10 Family Datasheet.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
---
 util/inteltool/gpio.c |   40 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 40 insertions(+), 0 deletions(-)
Nathan Williams - 2010-08-31 02:26:52
On Mon, 2010-08-30 at 18:52 -0700, Warren Turkal wrote:
> BTW, is there a git tree that is maintained and up to date? I'd rather
> not use git svn if I could avoid it.
> 
> Thanks,
> wt

Hi Warren,

I have a hourly cron job keeping this git tree updated:

git://github.com/ngwill/coreboot.git

Regards,
Nathan
Warren Turkal - 2010-09-01 01:13:52
Thanks,
wt

On Mon, Aug 30, 2010 at 7:26 PM, Nathan Williams <nathan@traverse.com.au> wrote:
> On Mon, 2010-08-30 at 18:52 -0700, Warren Turkal wrote:
>> BTW, is there a git tree that is maintained and up to date? I'd rather
>> not use git svn if I could avoid it.
>>
>> Thanks,
>> wt
>
> Hi Warren,
>
> I have a hourly cron job keeping this git tree updated:
>
> git://github.com/ngwill/coreboot.git
>
> Regards,
> Nathan
>
>
Warren Turkal - 2010-09-01 01:15:33
BTW, any reason not to add this info the wiki somewhere?

Thanks,
wt

On Tue, Aug 31, 2010 at 6:13 PM, Warren Turkal <wt@penguintechs.org> wrote:
> Thanks,
> wt
>
> On Mon, Aug 30, 2010 at 7:26 PM, Nathan Williams <nathan@traverse.com.au> wrote:
>> On Mon, 2010-08-30 at 18:52 -0700, Warren Turkal wrote:
>>> BTW, is there a git tree that is maintained and up to date? I'd rather
>>> not use git svn if I could avoid it.
>>>
>>> Thanks,
>>> wt
>>
>> Hi Warren,
>>
>> I have a hourly cron job keeping this git tree updated:
>>
>> git://github.com/ngwill/coreboot.git
>>
>> Regards,
>> Nathan
>>
>>
>
Corey Osgood - 2010-09-01 03:42:00
On Mon, Aug 30, 2010 at 9:52 PM, Warren Turkal <wt@penguintechs.org> wrote:
> I clearly included the patch without my sign off. Here's another
> exported from my git tree.

Acked-by: Corey Osgood <corey.osgood@gmail.com>

And committed in r5761.

Is RCBA/ACPI support in the works?

-Corey
Warren Turkal - 2010-09-01 09:18:10
On Tue, Aug 31, 2010 at 8:42 PM, Corey Osgood <corey.osgood@gmail.com> wrote:
> Is RCBA/ACPI support in the works?

I'm about to send the RCBA support.

Thanks,
wt

Patch

diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 75658a9..9bb23c9 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -152,6 +152,41 @@  static const io_register_t ich9_gpio_registers[] = {
 	{ 0x3C, 4, "RESERVED" }
 };
 
+static const io_register_t ich10_gpio_registers[] = {
+	{ 0x00, 4, "GPIO_USE_SEL" },
+	{ 0x04, 4, "GP_IO_SEL" },
+	{ 0x08, 4, "RESERVED" },
+	{ 0x0c, 4, "GP_LVL" },
+	{ 0x10, 4, "RESERVED" },
+	{ 0x14, 4, "RESERVED" },
+	{ 0x18, 4, "GPO_BLINK" },
+	{ 0x1c, 4, "GP_SER_BLINK" },
+	{ 0x20, 4, "GP_SB_CMDSTS" },
+	{ 0x24, 4, "GP_SB_DATA" },
+	{ 0x28, 4, "RESERVED" },
+	{ 0x2c, 4, "GPI_INV" },
+	{ 0x30, 4, "GPIO_USE_SEL2" },
+	{ 0x34, 4, "GP_IO_SEL2" },
+	{ 0x38, 4, "GP_LVL2" },
+	{ 0x3C, 4, "RESERVED" },
+	{ 0x40, 4, "GPIO_USE_SEL3" },
+	{ 0x44, 4, "GPIO_SEL3" },
+	{ 0x48, 4, "GPIO_LVL3" },
+	{ 0x4c, 4, "RESERVED" },
+	{ 0x50, 4, "RESERVED" },
+	{ 0x54, 4, "RESERVED" },
+	{ 0x58, 4, "RESERVED" },
+	{ 0x5c, 4, "RESERVED" },
+	{ 0x60, 4, "GP_RST_SEL" },
+	{ 0x64, 4, "RESERVED" },
+	{ 0x68, 4, "RESERVED" },
+	{ 0x6c, 4, "RESERVED" },
+	{ 0x70, 4, "RESERVED" },
+	{ 0x74, 4, "RESERVED" },
+	{ 0x78, 4, "RESERVED" },
+	{ 0x7c, 4, "RESERVED" },
+};
+
 int print_gpios(struct pci_dev *sb)
 {
 	int i, size;
@@ -161,6 +196,11 @@  int print_gpios(struct pci_dev *sb)
 	printf("\n============= GPIOS =============\n\n");
 
 	switch (sb->device_id) {
+	case PCI_DEVICE_ID_INTEL_ICH10R:
+		gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+		gpio_registers = ich10_gpio_registers;
+		size = ARRAY_SIZE(ich10_gpio_registers);
+		break;
 	case PCI_DEVICE_ID_INTEL_ICH9DH:
 	case PCI_DEVICE_ID_INTEL_ICH9DO:
 	case PCI_DEVICE_ID_INTEL_ICH9R: