Submitter | She, Kerry |
---|---|
Date | 2010-09-03 10:13:27 |
Message ID | <F53A09371FB723428826B442A4B20A4103F7C856@sbjgexmb1.amd.com> |
Download | mbox | patch |
Permalink | /patch/1856/ |
State | Accepted |
Delegated to: | Patrick Georgi |
Headers | show |
Comments
Patch
Index: src/northbridge/amd/amdmct/mct/mct_d.c =================================================================== --- src/northbridge/amd/amdmct/mct/mct_d.c (revision 5773) +++ src/northbridge/amd/amdmct/mct/mct_d.c (working copy) @@ -3461,9 +3461,10 @@ i = 0; /* use i for the dct setting required */ if (pDCTstat->MAdimms[0] < 4) i = 1; - if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) + if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) { dword &= 0xF18FFF18; index_reg = 0x98; /* force dct = 0 */ + } } Set_NB32_index_wait(dev, index_reg, 0x0a, dword);
Hello, AMD DDR2 MCT function InitPhyCompensation() compliant with AGESA code. Signed-off-by: Kerry She <Kerry.she@amd.com>