| Submitter | Aurélien |
|---|---|
| Date | 2010-09-04 22:00:30 |
| Message ID | <AANLkTikpNu9YEN+WfNZK2mDRuT4X5i=3kygycu7oTqgw@mail.gmail.com> |
| Download | mbox | patch |
| Permalink | /patch/1864/ |
| State | Accepted |
| Headers | show |
Comments
Am 05.09.2010 00:00, schrieb Aurélien: > Geode LX RAMBASE @1M support: This one is in. I also removed RAMBASE from Alix.2d (which would be part of your second patch). > Alix.2[cd][23] support enhancements > ---- I'll leave this to someone else, who knows Alix better than I do. Thanks, Patrick
Hi, Could someone with Alix.2c or Alix.2d please review and ack/not ack this patch ? These are relatively trivial changes anyways. On Sun, Sep 5, 2010 at 12:00 AM, Aurélien <footplus@gmail.com> wrote: > > Alix.2[cd][23] support enhancements > ---- > !!!! Please $ svn mv alix2d alix2 before applying this patch. !!!! > I decided to rename the boards Alix.2 and support the following variants: > 2c2, 2c3, 2d2, 2d3, 2d13 - see help text -. 2d1 may also work, but differ > more: different ram size, and no USB, so I can't say. > I also added a submenu to configure which onboard LEDs should be lit at > boot. > Finally, I clarified the comments in irq_routing.c. > > On Tue, Sep 7, 2010 at 9:44 AM, Patrick Georgi <patrick@georgi-clan.de> wrote: > I'll leave this to someone else, who knows Alix better than I do. > Thanks :) Best regards,
Patch
Index: src/cpu/amd/model_lx/msrinit.c =================================================================== --- src/cpu/amd/model_lx/msrinit.c (revision 5766) +++ src/cpu/amd/model_lx/msrinit.c (working copy) @@ -39,6 +39,19 @@ {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF + + /* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory. + * It doesn't really matter in fact how much, however, because the only usage + * of this extended memory will be to host the coreboot_ram stage at RAMBASE, + * currently 1Mb. + * These registers will be set to their correct value by the Northbridge init code. + * + * WARNING: if coreboot_ram could not be loaded, these registers are probably + * incorrectly set here. You may comment the following two lines and set RAMBASE + * to 0x4000 to revert to the previous behavior for LX-boards. + */ + {MSR_GLIU0_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000 + {MSR_GLIU1_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000 }; static void msr_init(void) Index: src/mainboard/winent/pl6064/Kconfig =================================================================== --- src/mainboard/winent/pl6064/Kconfig (revision 5766) +++ src/mainboard/winent/pl6064/Kconfig (working copy) @@ -25,8 +25,4 @@ int default 7 -config RAMBASE - hex - default 0x4000 - endif # BOARD_WINENT_PL6064 Index: src/mainboard/lippert/roadrunner-lx/Kconfig =================================================================== --- src/mainboard/lippert/roadrunner-lx/Kconfig (revision 5766) +++ src/mainboard/lippert/roadrunner-lx/Kconfig (working copy) @@ -27,10 +27,6 @@ int default 7 -config RAMBASE - hex - default 0x4000 - config ONBOARD_UARTS_RS485 bool "Switch on-board serial ports to RS485" default n Index: src/mainboard/lippert/spacerunner-lx/Kconfig =================================================================== --- src/mainboard/lippert/spacerunner-lx/Kconfig (revision 5766) +++ src/mainboard/lippert/spacerunner-lx/Kconfig (working copy) @@ -28,10 +28,6 @@ int default 7 -config RAMBASE - hex - default 0x4000 - config ONBOARD_UARTS_RS485 bool "Switch on-board serial ports to RS485" default n Index: src/mainboard/artecgroup/dbe61/Kconfig =================================================================== --- src/mainboard/artecgroup/dbe61/Kconfig (revision 5766) +++ src/mainboard/artecgroup/dbe61/Kconfig (working copy) @@ -24,8 +24,4 @@ int default 3 -#config RAMBASE -# hex -# default 0x4000 - endif # BOARD_ARTECGROUP_DBE61 Index: src/mainboard/amd/norwich/Kconfig =================================================================== --- src/mainboard/amd/norwich/Kconfig (revision 5766) +++ src/mainboard/amd/norwich/Kconfig (working copy) @@ -24,8 +24,4 @@ int default 6 -config RAMBASE - hex - default 0x4000 - endif # BOARD_AMD_NORWICH Index: src/mainboard/amd/db800/Kconfig =================================================================== --- src/mainboard/amd/db800/Kconfig (revision 5766) +++ src/mainboard/amd/db800/Kconfig (working copy) @@ -25,8 +25,4 @@ int default 4 -config RAMBASE - hex - default 0x4000 - endif # BOARD_AMD_DB800 Index: src/mainboard/iei/pcisa-lx-800-r10/Kconfig =================================================================== --- src/mainboard/iei/pcisa-lx-800-r10/Kconfig (revision 5766) +++ src/mainboard/iei/pcisa-lx-800-r10/Kconfig (working copy) @@ -24,8 +24,4 @@ int default 9 -config RAMBASE - hex - default 0x4000 - endif # BOARD_IEI_PCISA_LX_800_R10 Index: src/mainboard/traverse/geos/Kconfig =================================================================== --- src/mainboard/traverse/geos/Kconfig (revision 5766) +++ src/mainboard/traverse/geos/Kconfig (working copy) @@ -24,8 +24,4 @@ int default 6 -config RAMBASE - hex - default 0x4000 - endif # BOARD_TRAVERSE_GEOS Index: src/mainboard/digitallogic/msm800sev/Kconfig =================================================================== --- src/mainboard/digitallogic/msm800sev/Kconfig (revision 5766) +++ src/mainboard/digitallogic/msm800sev/Kconfig (working copy) @@ -25,8 +25,4 @@ int default 9 -config RAMBASE - hex - default 0x4000 - endif # BOARD_DIGITALLOGIC_MSM800SEV Index: src/mainboard/pcengines/alix1c/Kconfig =================================================================== --- src/mainboard/pcengines/alix1c/Kconfig (revision 5766) +++ src/mainboard/pcengines/alix1c/Kconfig (working copy) @@ -25,8 +25,4 @@ int default 5 -config RAMBASE - hex - default 0x4000 - endif # BOARD_PCENGINES_ALIX1C
Hi everyone, Here are 2 patches: Geode LX RAMBASE @1M support: ---- Geode LX MSRs are now set up to allow early access to memory above 1Mb for loading coreboot_ram. An arbitrary amount (~500M) is set up, but is corrected shortly after, in the northbridge init code, so that should work in about every case on LX boards. I made modifications of RAMBASE to every board using LX northbridge, because the code setting the MSR access is done for all boards using LX. However, RAMBASE @0x4000 should still work in case of problems. Also added an explanation text about what is done. I only have Alix.2d13 board, so I can't say if this patch breaks things for other boards. Alix.2[cd][23] support enhancements ---- !!!! Please $ svn mv alix2d alix2 before applying this patch. !!!! I decided to rename the boards Alix.2 and support the following variants: 2c2, 2c3, 2d2, 2d3, 2d13 - see help text -. 2d1 may also work, but differ more: different ram size, and no USB, so I can't say. I also added a submenu to configure which onboard LEDs should be lit at boot. Finally, I clarified the comments in irq_routing.c. Please tell me what you think :) Signed-off-by: Aurélien Guillaume <aurelien@iwi.me> Best regards,