Patchwork [inteltool] renamed in bridgetool, added support of other non-Intel chipsets.

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Submitter Антон Кочков
Date 2010-09-05 15:55:45
Message ID <AANLkTinzQYo03BV0+PGD=qfdPaBP3N7ysFEUuqcQCG7v@mail.gmail.com>
Download mbox | patch
Permalink /patch/1866/
State New
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Антон Кочков - 2010-09-05 15:55:45
inteltool: renamed in bridgetool, added support of other chipsets.
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
---
Property changes on: .

Patch

Index: gpio.c
===================================================================
--- gpio.c	(revision 5777)
+++ gpio.c	(working copy)
@@ -1,5 +1,5 @@ 
 /*
- * inteltool - dump all registers on an Intel CPU + chipset based system.
+ * bridgetool - dump all chipset registers.
  *
  * Copyright (C) 2008 by coresystems GmbH
  *
@@ -18,7 +18,7 @@ 
  */
 
 #include <stdio.h>
-#include "inteltool.h"
+#include "bridgetool.h"
 
 static const io_register_t ich0_gpio_registers[] = {
 	{ 0x00, 4, "GPIO_USE_SEL" },
Index: inteltool.8
===================================================================
--- inteltool.8	(revision 5777)
+++ inteltool.8	(working copy)
@@ -1,67 +0,0 @@ 
-.TH INTELTOOL 8 "May 14, 2008"
-.SH NAME
-inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters
-.SH SYNOPSIS
-.B inteltool \fR[\fB\-vh?grpmedPMa\fR]
-.SH DESCRIPTION
-.B inteltool
-is a handy little tool for dumping the configuration space of Intel(R)
-CPUs, northbridges and southbridges.
-.sp
-This tool has been developed for the coreboot project (see
-.B http://coreboot.org
-for details on coreboot).
-.SH OPTIONS
-.TP
-.B "\-h, \-\-help"
-Show a help text and exit.
-.TP
-.B "\-v, \-\-version"
-Show version information and exit.
-.TP
-.B "\-a, \-\-all"
-Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge
-and Intel(R) Core CPU MSRs.
-.TP
-.B "\-g, \-\-gpio"
-Dump I/O Controller Hub (ICH) southbridge GPIO registers.
-.TP
-.B "\-r, \-\-rcba"
-Dump I/O Controller Hub (ICH) southbridge RCBA registers.
-.TP
-.B "\-p, \-\-pmbase"
-Dump I/O Controller Hub (ICH) southbridge PMBASE registers.
-.TP
-.B "\-m, \-\-mchbar"
-Dump Intel(R) northbridge MCHBAR registers.
-.TP
-.B "\-e, \-\-epbar"
-Dump Intel(R) northbridge EPBAR registers.
-.TP
-.B "\-d, \-\-dmibar"
-Dump Intel(R) northbridge DMIBAR registers.
-.TP
-.B "\-P, \-\-pciexbar"
-Dump Intel(R) northbridge PCIEXBAR registers.
-.TP
-.B "\-M, \-\-msrs"
-Dump Intel(R) CPU MSRs.
-.SH BUGS
-Please report any bugs at
-.BR http://tracker.coreboot.org/trac/coreboot/newticket ","
-or on the coreboot mailing list
-.RB "(" http://coreboot.org/Mailinglist ")."
-.SH LICENCE
-.B inteltool
-is covered by the GNU General Public License (GPL), version 2.
-.SH COPYRIGHT
-Copyright (C) 2008 coresystems GmbH
-.SH AUTHORS
-Stefan Reinauer <stepan@coresystems.de>
-.PP
-This manual page was written by Stefan Reinauer <stepan@coresystems.de>.
-It is licensed under the terms of the GNU GPL (version 2).
-.sp
-Intel(R) is a registered trademark of Intel Corporation. Other product
-and/or company names mentioned herein may be trademarks or registered
-trademarks of their respective owners.
Index: inteltool.h
===================================================================
--- inteltool.h	(revision 5777)
+++ inteltool.h	(working copy)
@@ -1,108 +0,0 @@ 
-/*
- * inteltool - dump all registers on an Intel CPU + chipset based system.
- *
- * Copyright (C) 2008-2010 by coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <stdint.h>
-
-#if defined(__GLIBC__)
-#include <sys/io.h>
-#endif
-#if (defined(__MACH__) && defined(__APPLE__))
-/* DirectIO is available here: http://www.coresystems.de/en/directio */
-#define __DARWIN__
-#include <DirectIO/darwinio.h>
-#endif
-#include <pci/pci.h>
-
-#define INTELTOOL_VERSION "1.0"
-
-/* Tested chipsets: */
-#define PCI_VENDOR_ID_INTEL			0x8086
-#define PCI_DEVICE_ID_INTEL_ICH			0x2410
-#define PCI_DEVICE_ID_INTEL_ICH0		0x2420
-#define PCI_DEVICE_ID_INTEL_ICH2		0x2440
-#define PCI_DEVICE_ID_INTEL_ICH4		0x24c0
-#define PCI_DEVICE_ID_INTEL_ICH4M		0x24cc
-#define PCI_DEVICE_ID_INTEL_ICH6		0x2640
-#define PCI_DEVICE_ID_INTEL_ICH7DH		0x27b0
-#define PCI_DEVICE_ID_INTEL_ICH7		0x27b8
-#define PCI_DEVICE_ID_INTEL_ICH7M		0x27b9
-#define PCI_DEVICE_ID_INTEL_ICH7MDH		0x27bd
-#define PCI_DEVICE_ID_INTEL_NM10		0x27bc
-#define PCI_DEVICE_ID_INTEL_ICH8		0x2810
-#define PCI_DEVICE_ID_INTEL_ICH8M		0x2815
-#define PCI_DEVICE_ID_INTEL_ICH9DH		0x2912
-#define PCI_DEVICE_ID_INTEL_ICH9DO		0x2914
-#define PCI_DEVICE_ID_INTEL_ICH9R		0x2916
-#define PCI_DEVICE_ID_INTEL_ICH9		0x2918
-#define PCI_DEVICE_ID_INTEL_ICH9M		0x2919
-#define PCI_DEVICE_ID_INTEL_ICH9ME		0x2917
-#define PCI_DEVICE_ID_INTEL_ICH10R		0x3a16
-#define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC	0x8119
-
-#define PCI_DEVICE_ID_INTEL_82810		0x7120
-#define PCI_DEVICE_ID_INTEL_82810DC		0x7122
-#define PCI_DEVICE_ID_INTEL_82810E_MC		0x7124
-#define PCI_DEVICE_ID_INTEL_82830M		0x3575
-#define PCI_DEVICE_ID_INTEL_82845		0x1a30
-#define PCI_DEVICE_ID_INTEL_82915		0x2580
-#define PCI_DEVICE_ID_INTEL_82945P		0x2770
-#define PCI_DEVICE_ID_INTEL_82945GM		0x27a0
-#define PCI_DEVICE_ID_INTEL_82945GSE		0x27ac
-#define PCI_DEVICE_ID_INTEL_PM965		0x2a00
-#define PCI_DEVICE_ID_INTEL_Q965		0x2990
-#define PCI_DEVICE_ID_INTEL_82975X		0x277c
-#define PCI_DEVICE_ID_INTEL_82Q35		0x29b0
-#define PCI_DEVICE_ID_INTEL_82G33		0x29c0
-#define PCI_DEVICE_ID_INTEL_82Q33		0x29d0
-#define PCI_DEVICE_ID_INTEL_GS45		0x2a40
-#define PCI_DEVICE_ID_INTEL_X58			0x3405
-#define PCI_DEVICE_ID_INTEL_SCH_POULSBO		0x8100
-#define PCI_DEVICE_ID_INTEL_ATOM_DXXX		0xa000
-
-/* untested, but almost identical to D-series */
-#define PCI_DEVICE_ID_INTEL_ATOM_NXXX		0xa010
-
-#define PCI_DEVICE_ID_INTEL_82443LX		0x7180
-/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
-#define PCI_DEVICE_ID_INTEL_82443BX		0x7190
-#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP	0x7192
-
-/* 82371AB/EB/MB use the same device ID value. */
-#define PCI_DEVICE_ID_INTEL_82371XX		0x7110
-
-#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
-
-#ifndef __DARWIN__
-typedef struct { uint32_t hi, lo; } msr_t;
-#endif
-typedef struct { uint16_t addr; int size; char *name; } io_register_t;
-
-void *map_physical(unsigned long phys_addr, size_t len);
-void unmap_physical(void *virt_addr, size_t len);
-
-unsigned int cpuid(unsigned int op);
-int print_intel_core_msrs(void);
-int print_mchbar(struct pci_dev *nb);
-int print_pmbase(struct pci_dev *sb);
-int print_rcba(struct pci_dev *sb);
-int print_gpios(struct pci_dev *sb);
-int print_epbar(struct pci_dev *nb);
-int print_dmibar(struct pci_dev *nb);
-int print_pciexbar(struct pci_dev *nb);
-
Index: bridgetool.h
===================================================================
--- bridgetool.h	(revision 5777)
+++ bridgetool.h	(working copy)
@@ -1,5 +1,5 @@ 
 /*
- * inteltool - dump all registers on an Intel CPU + chipset based system.
+ * bridgetool - dump all chipset registers.
  *
  * Copyright (C) 2008-2010 by coresystems GmbH
  *
@@ -29,9 +29,20 @@ 
 #endif
 #include <pci/pci.h>
 
-#define INTELTOOL_VERSION "1.0"
+#define BRIDGETOOL_VERSION "1.0"
 
+/* Chipset vendors: */
+#define PCI_VENDOR_ID_INTEL			0x8086
+#define PCI_VENDOR_ID_VIA			0x1106
+#define PCI_VENDOR_ID_ATI_AMD			0x1002
+#define PCI_VENDOR_ID_AMD			0x1022
+#define PCI_VENDOR_ID_SIS			0x1039
+#define PCI_VENDOR_ID_NVIDIA			0x10DE
+
 /* Tested chipsets: */
+
+/* INTEL CHIPSETS */
+
 #define PCI_VENDOR_ID_INTEL			0x8086
 #define PCI_DEVICE_ID_INTEL_ICH			0x2410
 #define PCI_DEVICE_ID_INTEL_ICH0		0x2420
@@ -86,6 +97,15 @@ 
 /* 82371AB/EB/MB use the same device ID value. */
 #define PCI_DEVICE_ID_INTEL_82371XX		0x7110
 
+/* VIA CHIPSETS */
+
+#define PCI_DEVICE_ID_VIA_VT8235		0x3059
+
+/* NVIDIA CHIPSETS */
+
+#define PCI_DEVICE_ID_NVIDIA_MCP		0x10D0
+
+
 #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
 
 #ifndef __DARWIN__
Index: bridgetool.8
===================================================================
--- bridgetool.8	(revision 5777)
+++ bridgetool.8	(working copy)
@@ -1,11 +1,11 @@ 
-.TH INTELTOOL 8 "May 14, 2008"
+.TH BRIDGETOOL 8 "May 14, 2008"
 .SH NAME
-inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters
+bridgetool \- a tool for dumping CPU / chipset configuration parameters
 .SH SYNOPSIS
-.B inteltool \fR[\fB\-vh?grpmedPMa\fR]
+.B bridgetool \fR[\fB\-vh?grpmedPMa\fR]
 .SH DESCRIPTION
-.B inteltool
-is a handy little tool for dumping the configuration space of Intel(R)
+.B bridgetool
+is a handy little tool for dumping the configuration space of
 CPUs, northbridges and southbridges.
 .sp
 This tool has been developed for the coreboot project (see
@@ -20,39 +20,39 @@ 
 Show version information and exit.
 .TP
 .B "\-a, \-\-all"
-Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge
-and Intel(R) Core CPU MSRs.
+Dump all known southbridge, northbridge
+and Core CPU MSRs.
 .TP
 .B "\-g, \-\-gpio"
-Dump I/O Controller Hub (ICH) southbridge GPIO registers.
+Dump southbridge GPIO registers.
 .TP
 .B "\-r, \-\-rcba"
-Dump I/O Controller Hub (ICH) southbridge RCBA registers.
+Dump southbridge RCBA registers.
 .TP
 .B "\-p, \-\-pmbase"
-Dump I/O Controller Hub (ICH) southbridge PMBASE registers.
+Dump southbridge PMBASE registers.
 .TP
 .B "\-m, \-\-mchbar"
-Dump Intel(R) northbridge MCHBAR registers.
+Dump northbridge MCHBAR registers.
 .TP
 .B "\-e, \-\-epbar"
-Dump Intel(R) northbridge EPBAR registers.
+Dump northbridge EPBAR registers.
 .TP
 .B "\-d, \-\-dmibar"
-Dump Intel(R) northbridge DMIBAR registers.
+Dump northbridge DMIBAR registers.
 .TP
 .B "\-P, \-\-pciexbar"
-Dump Intel(R) northbridge PCIEXBAR registers.
+Dump northbridge PCIEXBAR registers.
 .TP
 .B "\-M, \-\-msrs"
-Dump Intel(R) CPU MSRs.
+Dump CPU MSRs.
 .SH BUGS
 Please report any bugs at
 .BR http://tracker.coreboot.org/trac/coreboot/newticket ","
 or on the coreboot mailing list
 .RB "(" http://coreboot.org/Mailinglist ")."
 .SH LICENCE
-.B inteltool
+.B bridgetool
 is covered by the GNU General Public License (GPL), version 2.
 .SH COPYRIGHT
 Copyright (C) 2008 coresystems GmbH
Index: pcie.c
===================================================================
--- pcie.c	(revision 5777)
+++ pcie.c	(working copy)
@@ -1,5 +1,5 @@ 
 /*
- * inteltool - dump all registers on an Intel CPU + chipset based system.
+ * bridgetool - dump all chipset registers.
  *
  * Copyright (C) 2008-2010 by coresystems GmbH
  *
@@ -19,7 +19,7 @@ 
 
 #include <stdio.h>
 #include <stdlib.h>
-#include "inteltool.h"
+#include "bridgetool.h"
 
 /*
  * Egress Port Root Complex MMIO configuration space
Index: powermgt.c
===================================================================
--- powermgt.c	(revision 5777)
+++ powermgt.c	(working copy)
@@ -1,5 +1,5 @@ 
 /*
- * inteltool - dump all registers on an Intel CPU + chipset based system.
+ * bridgetool - dump all chipset registers.
  *
  * Copyright (C) 2008-2010 by coresystems GmbH
  *  written by Stefan Reinauer <stepan@coresystems.de>
@@ -19,7 +19,7 @@ 
  */
 
 #include <stdio.h>
-#include "inteltool.h"
+#include "bridgetool.h"
 
 static const io_register_t ich10_pm_registers[] = {
 	{ 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
Index: cpu.c
===================================================================
--- cpu.c	(revision 5777)
+++ cpu.c	(working copy)
@@ -1,5 +1,5 @@ 
 /*
- * inteltool - dump all registers on an Intel CPU + chipset based system.
+ * bridgetool - dump all chipset registers.
  *
  * Copyright (C) 2008-2010 by coresystems GmbH
  *
@@ -24,7 +24,7 @@ 
 #include <string.h>
 #include <errno.h>
 
-#include "inteltool.h"
+#include "bridgetool.h"
 
 int fd_msr;
 
@@ -311,7 +311,7 @@ 
 	/*
 	 * All MSRs per
 	 *
-	 * Intel® 64 and IA-32 Architectures
+	 * Intel� 64 and IA-32 Architectures
 	 * Software Developer.s Manual
 	 * Volume 3B:
 	 * System Programming Guide, Part 2
Index: rootcmplx.c
===================================================================
--- rootcmplx.c	(revision 5777)
+++ rootcmplx.c	(working copy)
@@ -1,5 +1,5 @@ 
 /*
- * inteltool - dump all registers on an Intel CPU + chipset based system.
+ * bridgetool - dump all chipset registers.
  *
  * Copyright (C) 2008 by coresystems GmbH
  *  written by Stefan Reinauer <stepan@coresystems.de>
@@ -20,7 +20,7 @@ 
 
 #include <stdio.h>
 #include <stdlib.h>
-#include "inteltool.h"
+#include "bridgetool.h"
 
 int print_rcba(struct pci_dev *sb)
 {
Index: memory.c
===================================================================
--- memory.c	(revision 5777)
+++ memory.c	(working copy)
@@ -1,5 +1,5 @@ 
 /*
- * inteltool - dump all registers on an Intel CPU + chipset based system.
+ * bridgetool - dump all chipset registers.
  *
  * Copyright (C) 2008-2010 by coresystems GmbH
  *
@@ -20,7 +20,7 @@ 
 
 #include <stdio.h>
 #include <stdlib.h>
-#include "inteltool.h"
+#include "bridgetool.h"
 
 /*
  * (G)MCH MMIO Config Space
Index: inteltool.c
===================================================================
--- inteltool.c	(revision 5777)
+++ inteltool.c	(working copy)
@@ -1,346 +0,0 @@ 
-/*
- * inteltool - dump all registers on an Intel CPU + chipset based system.
- *
- * Copyright (C) 2008-2010 by coresystems GmbH
- *  written by Stefan Reinauer <stepan@coresystems.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <getopt.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-#include "inteltool.h"
-
-static const struct {
-	uint16_t vendor_id, device_id;
-	char *name;
-} supported_chips_list[] = {
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "i945GSE" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, 
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9R, "ICH9R" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9, "ICH9" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8, "ICH8" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10, "NM10" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6, "ICH6" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
-};
-
-#ifndef __DARWIN__
-static int fd_mem;
-
-void *map_physical(unsigned long phys_addr, size_t len)
-{
-	void *virt_addr;
-
-	virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED,
-		    fd_mem, (off_t) phys_addr);
-
-	if (virt_addr == MAP_FAILED) {
-		printf("Error mapping physical memory 0x%08lx[0x%x]\n", phys_addr, len);
-		return NULL;
-	}
-
-	return virt_addr;
-}
-
-void unmap_physical(void *virt_addr, size_t len)
-{
-	munmap(virt_addr, len);
-}
-#endif
-
-void print_version(void)
-{
-	printf("inteltool v%s -- ", INTELTOOL_VERSION);
-	printf("Copyright (C) 2008 coresystems GmbH\n\n");
-	printf(
-    "This program is free software: you can redistribute it and/or modify\n"
-    "it under the terms of the GNU General Public License as published by\n"
-    "the Free Software Foundation, version 2 of the License.\n\n"
-    "This program is distributed in the hope that it will be useful,\n"
-    "but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
-    "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n"
-    "GNU General Public License for more details.\n\n"
-    "You should have received a copy of the GNU General Public License\n"
-    "along with this program.  If not, see <http://www.gnu.org/licenses/>.\n\n");
-}
-
-void print_usage(const char *name)
-{
-	printf("usage: %s [-vh?grpmedPMa]\n", name);
-	printf("\n"
-	     "   -v | --version:                   print the version\n"
-	     "   -h | --help:                      print this help\n\n"
-	     "   -g | --gpio:                      dump soutbridge GPIO registers\n"
-	     "   -r | --rcba:                      dump soutbridge RCBA registers\n"
-	     "   -p | --pmbase:                    dump soutbridge Power Management registers\n\n"
-	     "   -m | --mchbar:                    dump northbridge Memory Controller registers\n"
-	     "   -e | --epbar:                     dump northbridge EPBAR registers\n"
-	     "   -d | --dmibar:                    dump northbridge DMIBAR registers\n"
-	     "   -P | --pciexpress:                dump northbridge PCIEXBAR registers\n\n"
-	     "   -M | --msrs:                      dump CPU MSRs\n"
-	     "   -a | --all:                       dump all known registers\n"
-	     "\n");
-	exit(1);
-}
-
-int main(int argc, char *argv[])
-{
-	struct pci_access *pacc;
-	struct pci_dev *sb = NULL, *nb, *dev;
-	int i, opt, option_index = 0;
-	unsigned int id;
-
-	char *sbname = "unknown", *nbname = "unknown";
-
-	int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0;
-	int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0;
-	int dump_pciexbar = 0, dump_coremsrs = 0;
-
-	static struct option long_options[] = {
-		{"version", 0, 0, 'v'},
-		{"help", 0, 0, 'h'},
-		{"gpios", 0, 0, 'g'},
-		{"mchbar", 0, 0, 'm'},
-		{"rcba", 0, 0, 'r'},
-		{"pmbase", 0, 0, 'p'},
-		{"epbar", 0, 0, 'e'},
-		{"dmibar", 0, 0, 'd'},
-		{"pciexpress", 0, 0, 'P'},
-		{"msrs", 0, 0, 'M'},
-		{"all", 0, 0, 'a'},
-		{0, 0, 0, 0}
-	};
-
-	while ((opt = getopt_long(argc, argv, "vh?grpmedPMa",
-                                  long_options, &option_index)) != EOF) {
-		switch (opt) {
-		case 'v':
-			print_version();
-			exit(0);
-			break;
-		case 'g':
-			dump_gpios = 1;
-			break;
-		case 'm':
-			dump_mchbar = 1;
-			break;
-		case 'r':
-			dump_rcba = 1;
-			break;
-		case 'p':
-			dump_pmbase = 1;
-			break;
-		case 'e':
-			dump_epbar = 1;
-			break;
-		case 'd':
-			dump_dmibar = 1;
-			break;
-		case 'P':
-			dump_pciexbar = 1;
-			break;
-		case 'M':
-			dump_coremsrs = 1;
-			break;
-		case 'a':
-			dump_gpios = 1;
-			dump_mchbar = 1;
-			dump_rcba = 1;
-			dump_pmbase = 1;
-			dump_epbar = 1;
-			dump_dmibar = 1;
-			dump_pciexbar = 1;
-			dump_coremsrs = 1;
-			break;
-		case 'h':
-		case '?':
-		default:
-			print_usage(argv[0]);
-			exit(0);
-			break;
-		}
-	}
-
-	if (iopl(3)) {
-		printf("You need to be root.\n");
-		exit(1);
-	}
-
-#ifndef __DARWIN__
-	if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) {
-		perror("Can not open /dev/mem");
-		exit(1);
-	}
-#endif
-
-	pacc = pci_alloc();
-	pci_init(pacc);
-	pci_scan_bus(pacc);
-
-	/* Find the required devices */
-	for (dev = pacc->devices; dev; dev = dev->next) {
-		pci_fill_info(dev, PCI_FILL_CLASS);
-		/* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */
-		if (dev->device_class == 0x0601) { /* ISA/LPC bridge */
-			if (sb == NULL)
-				sb = dev;
-			else
-				fprintf(stderr, "Multiple devices with class ID"
-					" 0x0601, using %02x%02x:%02x.%02x\n",
-					dev->domain, dev->bus, dev->dev,
-					dev->func);
-		}
-	}
-
-	if (!sb) {
-		printf("No southbridge found.\n");
-		exit(1);
-	}
-
-	pci_fill_info(sb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
-
-	if (sb->vendor_id != PCI_VENDOR_ID_INTEL) {
-		printf("Not an Intel(R) southbridge.\n");
-		exit(1);
-	}
-
-	nb = pci_get_dev(pacc, 0, 0, 0x00, 0);
-	if (!nb) {
-		printf("No northbridge found.\n");
-		exit(1);
-	}
-
-	pci_fill_info(nb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
-
-	if (nb->vendor_id != PCI_VENDOR_ID_INTEL) {
-		printf("Not an Intel(R) northbridge.\n");
-		exit(1);
-	}
-
-	id = cpuid(1);
-
-	/* Intel has suggested applications to display the family of a CPU as
-	 * the sum of the "Family" and the "Extended Family" fields shown
-	 * above, and the model as the sum of the "Model" and the 4-bit
-	 * left-shifted "Extended Model" fields.
-	 * http://download.intel.com/design/processor/applnots/24161832.pdf
-	 */
-	printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n",
-			(id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff),
-			((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf));
-
-	/* Determine names */
-	for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
-		if (nb->device_id == supported_chips_list[i].device_id)
-			nbname = supported_chips_list[i].name;
-	for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
-		if (sb->device_id == supported_chips_list[i].device_id)
-			sbname = supported_chips_list[i].name;
-
-	printf("Intel Northbridge: %04x:%04x (%s)\n",
-		nb->vendor_id, nb->device_id, nbname);
-
-	printf("Intel Southbridge: %04x:%04x (%s)\n",
-		sb->vendor_id, sb->device_id, sbname);
-
-	/* Now do the deed */
-
-	if (dump_gpios) {
-		print_gpios(sb);
-		printf("\n\n");
-	}
-
-	if (dump_rcba) {
-		print_rcba(sb);
-		printf("\n\n");
-	}
-
-	if (dump_pmbase) {
-		print_pmbase(sb);
-		printf("\n\n");
-	}
-
-	if (dump_mchbar) {
-		print_mchbar(nb);
-		printf("\n\n");
-	}
-
-	if (dump_epbar) {
-		print_epbar(nb);
-		printf("\n\n");
-	}
-
-	if (dump_dmibar) {
-		print_dmibar(nb);
-		printf("\n\n");
-	}
-
-	if (dump_pciexbar) {
-		print_pciexbar(nb);
-		printf("\n\n");
-	}
-
-	if (dump_coremsrs) {
-		print_intel_core_msrs();
-		printf("\n\n");
-	}
-
-	/* Clean up */
-	pci_free_dev(nb);
-	// pci_free_dev(sb); // TODO: glibc detected "double free or corruption"
-	pci_cleanup(pacc);
-
-	return 0;
-}
Index: bridgetool.c
===================================================================
--- bridgetool.c	(revision 5777)
+++ bridgetool.c	(working copy)
@@ -1,5 +1,5 @@ 
 /*
- * inteltool - dump all registers on an Intel CPU + chipset based system.
+ * bridgetool - dump all chipset registers.
  *
  * Copyright (C) 2008-2010 by coresystems GmbH
  *  written by Stefan Reinauer <stepan@coresystems.de>
@@ -23,12 +23,27 @@ 
 #include <getopt.h>
 #include <fcntl.h>
 #include <sys/mman.h>
-#include "inteltool.h"
+#include "bridgetool.h"
 
 static const struct {
+	uint16_t vendor_id;
+	char *name;
+} supported_vendor_list[] = {
+    { PCI_VENDOR_ID_INTEL, "Intel" },
+    { PCI_VENDOR_ID_VIA, "VIA" },
+    { PCI_VENDOR_ID_SIS, "SIS" },
+    { PCI_VENDOR_ID_ATI_AMD, "ATI/AMD" },
+    { PCI_VENDOR_ID_AMD, "AMD" },
+    { PCI_VENDOR_ID_NVIDIA, "NVIDIA" },
+};
+
+static const struct {
 	uint16_t vendor_id, device_id;
 	char *name;
 } supported_chips_list[] = {
+
+	/* INTEL CHIPSETS */
+    
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
@@ -74,6 +89,8 @@ 
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
+	
+	/* VIA CHIPSETS */
 };
 
 #ifndef __DARWIN__
@@ -102,7 +119,7 @@ 
 
 void print_version(void)
 {
-	printf("inteltool v%s -- ", INTELTOOL_VERSION);
+	printf("bridgetool v%s -- ", BRIDGETOOL_VERSION);
 	printf("Copyright (C) 2008 coresystems GmbH\n\n");
 	printf(
     "This program is free software: you can redistribute it and/or modify\n"
@@ -142,7 +159,7 @@ 
 	int i, opt, option_index = 0;
 	unsigned int id;
 
-	char *sbname = "unknown", *nbname = "unknown";
+	char *sbname = "unknown", *nbname = "unknown", *nbvendor = "unknown", *sbvendor = "unknown";
 
 	int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0;
 	int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0;
@@ -251,9 +268,27 @@ 
 
 	pci_fill_info(sb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
 
-	if (sb->vendor_id != PCI_VENDOR_ID_INTEL) {
-		printf("Not an Intel(R) southbridge.\n");
-		exit(1);
+	switch (sb->vendor_id) {
+		case PCI_VENDOR_ID_INTEL:
+		    break;
+		case PCI_VENDOR_ID_VIA:
+		    printf("VIA southbridges not yet supported.\n");
+		    exit(1);
+		case PCI_VENDOR_ID_SIS:
+		    printf("SiS southbridges not yet supported.\n");
+		    exit(1);
+		case PCI_VENDOR_ID_NVIDIA:
+		    printf("NVIDIA southbridges not yet supported.\n");
+		    exit(1);
+		case PCI_VENDOR_ID_ATI_AMD:
+		    printf("ATI/AMD southbridges not yet supported.\n");
+		    exit(1);
+		case PCI_VENDOR_ID_AMD:
+		    printf("AMD southbridges not yet supported.\n");
+		    exit(1);
+		default:
+		    printf("Unknown southbridges not yet supported.\n");
+		    exit(1);
 	}
 
 	nb = pci_get_dev(pacc, 0, 0, 0x00, 0);
@@ -264,9 +299,27 @@ 
 
 	pci_fill_info(nb, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS);
 
-	if (nb->vendor_id != PCI_VENDOR_ID_INTEL) {
-		printf("Not an Intel(R) northbridge.\n");
-		exit(1);
+	switch (nb->vendor_id) {
+		case PCI_VENDOR_ID_INTEL:
+		    break;
+		case PCI_VENDOR_ID_VIA:
+		    printf("VIA northbridges not yet supported.\n");
+		    exit(1);
+		case PCI_VENDOR_ID_SIS:
+		    printf("SiS northbridges not yet supported.\n");
+		    exit(1);
+		case PCI_VENDOR_ID_NVIDIA:
+		    printf("NVIDIA northbridges not yet supported.\n");
+		    exit(1);
+		case PCI_VENDOR_ID_ATI_AMD:
+		    printf("ATI/AMD northbridges not yet supported.\n");
+		    exit(1);
+		case PCI_VENDOR_ID_AMD:
+		    printf("AMD northbridges not yet supported.\n");
+		    exit(1);
+		default:
+		    printf("Unknown northbridges not yet supported.\n");
+		    exit(1);
 	}
 
 	id = cpuid(1);
@@ -282,6 +335,12 @@ 
 			((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf));
 
 	/* Determine names */
+	for (i = 0; i < ARRAY_SIZE(supported_vendor_list); i++)
+		if (nb->vendor_id == supported_vendor_list[i].vendor_id)
+			nbvendor = supported_vendor_list[i].name;
+	for (i = 0; i < ARRAY_SIZE(supported_vendor_list); i++)
+		if (sb->vendor_id == supported_vendor_list[i].vendor_id)
+			sbvendor = supported_vendor_list[i].name;
 	for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++)
 		if (nb->device_id == supported_chips_list[i].device_id)
 			nbname = supported_chips_list[i].name;
@@ -289,12 +348,12 @@ 
 		if (sb->device_id == supported_chips_list[i].device_id)
 			sbname = supported_chips_list[i].name;
 
-	printf("Intel Northbridge: %04x:%04x (%s)\n",
-		nb->vendor_id, nb->device_id, nbname);
+	printf("Northbridge: %04x:%04x | Vendor: %s | Model: %s\n",
+		nb->vendor_id, nb->device_id, nbvendor, nbname);
 
-	printf("Intel Southbridge: %04x:%04x (%s)\n",
-		sb->vendor_id, sb->device_id, sbname);
-
+	printf("Southbridge: %04x:%04x | Vendor: %s | Model: %s\n",
+		sb->vendor_id, sb->device_id, sbvendor, sbname);
+	
 	/* Now do the deed */
 
 	if (dump_gpios) {
Index: Makefile
===================================================================
--- Makefile	(revision 5777)
+++ Makefile	(working copy)
@@ -1,5 +1,5 @@ 
 #
-# Makefile for inteltool utility
+# Makefile for bridgetool utility
 #
 # Copyright (C) 2008 by coresystems GmbH
 # written by Stefan Reinauer <stepan@coresystems.de>
@@ -19,7 +19,7 @@ 
 # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 #
 
-PROGRAM = inteltool
+PROGRAM = bridgetool
 
 CC      = gcc
 INSTALL = /usr/bin/install
@@ -27,7 +27,7 @@ 
 CFLAGS  = -O2 -g -Wall -W
 LDFLAGS = -lpci -lz
 
-OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o
+OBJS = bridgetool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o
 
 OS_ARCH	= $(shell uname)
 ifeq ($(OS_ARCH), Darwin)