From patchwork Mon Sep 6 23:24:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [3/4] Reduce TSC calibrations from 20ms to 2ms. Date: Mon, 06 Sep 2010 23:24:11 -0000 From: Kevin O'Connor X-Patchwork-Id: 1877 Message-Id: <7986f0442d0e6007a1d479241229158fc4f902b9.1283815188.git.kevin@koconnor.net> To: coreboot@coreboot.org 2ms is enough time to accurately obtain the clock rate. Signed-off-by: Kevin O'Connor Acked-by: Patrick Georgi --- src/cpu/x86/tsc/delay_tsc.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 27c89e3..1127867 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -18,8 +18,8 @@ static unsigned long clocks_per_usec; * device. */ -#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */ -#define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */ +#define CALIBRATE_INTERVAL ((2*CLOCK_TICK_RATE)/1000) /* 2ms */ +#define CALIBRATE_DIVISOR (2*1000) /* 2ms / 2000 == 1usec */ static unsigned long long calibrate_tsc(void) {