Patchwork AMD MMCONF Support

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Submitter Arne Georg Gleditsch
Date 2010-09-08 13:53:27
Message ID <87lj7ctk88.fsf@taniquetil.gledits.ch>
Download mbox | patch
Permalink /patch/1889/
State Superseded
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Comments

Arne Georg Gleditsch - 2010-09-08 13:53:27
Arne Georg Gleditsch <arne.gleditsch@numascale.com> writes:
> I intend to rework the MMCONF patch to map the MMCONF area into 32-bit
> address space, [..]

Please find appended.  This patch gets rid of the %gs magic altogether,
fixes a few alignment wrinkles and sets up and registers the MMCONF area
for AMD Fam10h CPUs (where selected by mainboard configuration).  It
removes a bit of code that proved troublesome in MMCONF setups from
mcp55_early_setup_car.c, as per earlier discussion.

(The way the patch hooks add_northbridge_resources via
s2912_fam10/mainboard.c replicates a well-used pattern that perhaps
ought to be simplified.  HAVE_NORTHBRIDGE_RESOURCES would remove
otherwise empty add_mainboard_resources from a lot of mainboard.c
files.)

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Myles Watson - 2010-09-08 14:40:38
On Wed, Sep 8, 2010 at 7:53 AM, Arne Georg Gleditsch
<arne.gleditsch@numascale.com> wrote:
> Arne Georg Gleditsch <arne.gleditsch@numascale.com> writes:
>> I intend to rework the MMCONF patch to map the MMCONF area into 32-bit
>> address space, [..]
>
> Please find appended.  This patch gets rid of the %gs magic altogether,
> fixes a few alignment wrinkles and sets up and registers the MMCONF area
> for AMD Fam10h CPUs (where selected by mainboard configuration).  It
> removes a bit of code that proved troublesome in MMCONF setups from
> mcp55_early_setup_car.c, as per earlier discussion.
>
> (The way the patch hooks add_northbridge_resources via
> s2912_fam10/mainboard.c replicates a well-used pattern that perhaps
> ought to be simplified.  HAVE_NORTHBRIDGE_RESOURCES would remove
> otherwise empty add_mainboard_resources from a lot of mainboard.c
> files.)
I'm confused why you wouldn't add the resource from the northbridge
code.  Is there a reason to have it be a mainboard resource?

+config MMCONF_SUPPORT
+	bool
+	default y
+	depends on NORTHBRIDGE_AMD_AMDFAM10

You could use select for MMCONF_SUPPORT.  I think it should be
selected in the northbridge or in the mainboard, but not both.

Instead of adding the reserved area directly to the coreboot tables,
you should add it before resource allocation and let the rest happen
automatically.

Thanks,
Myles
Arne Georg Gleditsch - 2010-09-08 15:00:18
Myles Watson <mylesgw@gmail.com> writes:
> I'm confused why you wouldn't add the resource from the northbridge
> code.  Is there a reason to have it be a mainboard resource?

Not really, but there's no existing infrastructure for having
add_northbridge_resources be called except by way of
add_mainboard_resources.  As far as I can tell.  I think this may
warrant changing, but preferrably as a separate step.

> +config MMCONF_SUPPORT
> +	bool
> +	default y
> +	depends on NORTHBRIDGE_AMD_AMDFAM10
>
> You could use select for MMCONF_SUPPORT.  I think it should be
> selected in the northbridge or in the mainboard, but not both.

MMCONF_SUPPORT is selected in the northbridge, MMCONF_SUPPORT_DEFAULT is
selected in the mainboard config to actually activate the functionality.
This was the way I read the existing code, perhaps this two-level
approach is not be required?  Either way, I think you want to select
this on a mainboard-by-mainboard basis, at least initially.  There is a
potential for breakage, like the one we experienced with the nvidia
southbridge.

> Instead of adding the reserved area directly to the coreboot tables,
> you should add it before resource allocation and let the rest happen
> automatically.

I'm sorry, I'm not at all familiar with the resource allocation
framework.  I tried to model this on the corresponding code for relevant
Intel mainboards.  How would you change it, precisely?
Myles Watson - 2010-09-08 16:04:16
On Wed, Sep 8, 2010 at 9:00 AM, Arne Georg Gleditsch
<arne.gleditsch@numascale.com> wrote:
> Myles Watson <mylesgw@gmail.com> writes:
>> I'm confused why you wouldn't add the resource from the northbridge
>> code.  Is there a reason to have it be a mainboard resource?
>
> Not really, but there's no existing infrastructure for having
> add_northbridge_resources be called except by way of
> add_mainboard_resources.  As far as I can tell.  I think this may
> warrant changing, but preferrably as a separate step.
>
>> +config MMCONF_SUPPORT
>> +     bool
>> +     default y
>> +     depends on NORTHBRIDGE_AMD_AMDFAM10
>>
>> You could use select for MMCONF_SUPPORT.  I think it should be
>> selected in the northbridge or in the mainboard, but not both.
>
> MMCONF_SUPPORT is selected in the northbridge, MMCONF_SUPPORT_DEFAULT is
> selected in the mainboard config to actually activate the functionality.
> This was the way I read the existing code, perhaps this two-level
> approach is not be required?  Either way, I think you want to select
> this on a mainboard-by-mainboard basis, at least initially.  There is a
> potential for breakage, like the one we experienced with the nvidia
> southbridge.
OK.

>> Instead of adding the reserved area directly to the coreboot tables,
>> you should add it before resource allocation and let the rest happen
>> automatically.
>
> I'm sorry, I'm not at all familiar with the resource allocation
> framework.  I tried to model this on the corresponding code for relevant
> Intel mainboards.  How would you change it, precisely?
Fair question.  It's been a long time since I've thought about MMCONF,
but here are a couple of ways that I think it could be done:

I. Use a hard-coded address for MMCONF only for pre-RAM
1. Add a resource to read_resources in the northbridge that gives the
size but isn't fixed
2. The resource allocator will find a good place for it
3. In set resource update the address so that future accesses work

II. Use a hard-coded fixed address always
1. Add a fixed resource to read_resources in the northbridge
2. The resource allocator will avoid it

Either way, if the area needs to end up reserved in the coreboot
tables, then the code should live there.  If we need a new resource
flag that says create an entry for this, then I think that would be
the way to go.  I nominate IORESOURCE_RESERVE.

I started a patch that applied over yours, but I think discussing the
way to go in higher-level terms is the right first step.

Much of your patch is unrelated to this discussion.  If we split the
bug fixes into a separate patch and get that committed I'd be happy to
help make this work.

Thanks,
Myles
Myles Watson - 2010-09-08 16:48:53
>> Instead of adding the reserved area directly to the coreboot tables,
>> you should add it before resource allocation and let the rest happen
>> automatically.
>
> I'm sorry, I'm not at all familiar with the resource allocation
> framework.  I tried to model this on the corresponding code for relevant
> Intel mainboards.  How would you change it, precisely?
I'd forgotten that this was the way it was done.  I agree that you did
it the same way that it had been done before.  It's often hard to
review a patch without reviewing the mechanisms it uses.

Thanks,
Myles

Patch

diff --git a/src/arch/i386/include/arch/mmio_conf.h b/src/arch/i386/include/arch/mmio_conf.h
index df91cb5..08962f0 100644
--- a/src/arch/i386/include/arch/mmio_conf.h
+++ b/src/arch/i386/include/arch/mmio_conf.h
@@ -2,13 +2,13 @@ 
 #define ARCH_MMIO_H 1
 
 
-//extended read, GS is already set
+// Extended read, constrain to use registers as mandated by AMD MMCONFIG mechanism.
 
 static inline __attribute__((always_inline)) uint8_t read8x(uint32_t addr)
 {
 	uint8_t value;
         __asm__ volatile (
-                "movb %%gs:(%1), %0\n\t"
+                "movb (%1), %%al\n\t"
                 :"=a"(value): "b" (addr)
         );
         return value;
@@ -18,7 +18,7 @@  static inline __attribute__((always_inline)) uint16_t read16x(uint32_t addr)
 {
         uint16_t value;
         __asm__ volatile (
-                "movw %%gs:(%1), %0\n\t"
+                "movw (%1), %%ax\n\t"
                 :"=a"(value): "b" (addr)
         );
 
@@ -30,7 +30,7 @@  static inline __attribute__((always_inline)) uint32_t read32x(uint32_t addr)
 {
         uint32_t value;
         __asm__ volatile (
-                "movl %%gs:(%1), %0\n\t"
+                "movl (%1), %%eax\n\t"
                 :"=a"(value): "b" (addr)
         );
 
@@ -41,7 +41,7 @@  static inline __attribute__((always_inline)) uint32_t read32x(uint32_t addr)
 static inline __attribute__((always_inline)) void write8x(uint32_t addr, uint8_t value)
 {
         __asm__ volatile (
-                "movb %1, %%gs:(%0)\n\t"
+                "movb %%al, (%0)\n\t"
                 :: "b" (addr), "a" (value)
         );
 
@@ -50,7 +50,7 @@  static inline __attribute__((always_inline)) void write8x(uint32_t addr, uint8_t
 static inline __attribute__((always_inline)) void write16x(uint32_t addr, uint16_t value)
 {
         __asm__ volatile (
-                "movw %1, %%gs:(%0)\n\t"
+                "movw %%ax, (%0)\n\t"
                 :: "b" (addr), "a" (value)
         );
 
@@ -59,7 +59,7 @@  static inline __attribute__((always_inline)) void write16x(uint32_t addr, uint16
 static inline __attribute__((always_inline)) void write32x(uint32_t addr, uint32_t value)
 {
         __asm__ volatile (
-                "movl %1, %%gs:(%0)\n\t"
+                "movl %%eax, (%0)\n\t"
                 :: "b" (addr), "a" (value)
         );
 }
diff --git a/src/arch/i386/include/arch/romcc_io.h b/src/arch/i386/include/arch/romcc_io.h
index 6bc7dfc..79ea265 100644
--- a/src/arch/i386/include/arch/romcc_io.h
+++ b/src/arch/i386/include/arch/romcc_io.h
@@ -107,7 +107,7 @@  static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(devic
 static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
 {
         unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1);
         return read16x(addr);
 }
 #endif
@@ -138,7 +138,7 @@  static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(devic
 static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
 {
         unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3);
         return read32x(addr);
 }
 #endif
@@ -199,7 +199,7 @@  static inline __attribute__((always_inline)) void pci_io_write_config16(device_t
 static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value)
 {
         unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1);
         write16x(addr, value);
 }
 #endif
@@ -230,7 +230,7 @@  static inline __attribute__((always_inline)) void pci_io_write_config32(device_t
 static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value)
 {
         unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3);
         write32x(addr, value);
 }
 #endif
diff --git a/src/arch/i386/lib/pci_ops_mmconf.c b/src/arch/i386/lib/pci_ops_mmconf.c
index a605708..7d8fb32 100644
--- a/src/arch/i386/lib/pci_ops_mmconf.c
+++ b/src/arch/i386/lib/pci_ops_mmconf.c
@@ -27,12 +27,12 @@  static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, int
 
 static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, int where)
 {
-                return (read16x(PCI_MMIO_ADDR(bus, devfn, where)));
+                return (read16x(PCI_MMIO_ADDR(bus, devfn, where) & ~1));
 }
 
 static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, int where)
 {
-                return (read32x(PCI_MMIO_ADDR(bus, devfn, where)));
+                return (read32x(PCI_MMIO_ADDR(bus, devfn, where) & ~3));
 }
 
 static void  pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value)
@@ -42,12 +42,12 @@  static void  pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, int
 
 static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value)
 {
-                write8x(PCI_MMIO_ADDR(bus, devfn, where), value);
+                write16x(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value);
 }
 
 static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value)
 {
-                write8x(PCI_MMIO_ADDR(bus, devfn, where), value);
+                write32x(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value);
 }
 
 
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index a499f5f..11dea97 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -57,32 +57,28 @@  static void set_EnableCf8ExtCfg(void)
 static void set_EnableCf8ExtCfg(void) { }
 #endif
 
-/*[39:8] */
-#define PCI_MMIO_BASE 0xfe000000
-/* because we will use gs to store hi, so need to make sure lo can start
-   from 0, So PCI_MMIO_BASE & 0x00ffffff should be equal to 0*/
+
+#define _ULLx(x) x ## ULL
+#define _ULL(x) _ULLx(x)
+
+/*[63:0] */
+#define PCI_MMIO_BASE _ULL(CONFIG_MMCONF_BASE_ADDRESS)
 
 static void set_pci_mmio_conf_reg(void)
 {
 #if CONFIG_MMCONF_SUPPORT
+#  if PCI_MMIO_BASE > 0xffffffff
+#    error CONFIG_MMCONF_BASE_ADDRESS must currently fit in 32 bits!
+#  endif
 	msr_t msr;
 	msr = rdmsr(0xc0010058);
 	msr.lo &= ~(0xfff00000 | (0xf << 2));
-	// 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space
-	msr.lo |= ((8 + CONFIG_PCI_BUS_SEGN_BITS) << 2) | (1 << 0);
+	// 256 buses, one segment. Total 256M address space.
+	msr.lo |= (PCI_MMIO_BASE & 0xfff00000) | (8 << 2) | (1 << 0);
 	msr.hi &= ~(0x0000ffff);
-	msr.hi |= (PCI_MMIO_BASE >> (32 - 8));
-	wrmsr(0xc0010058, msr);	// MMIO Config Base Address Reg
-
-	//mtrr for that range?
-	// set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
-
-	set_wrap32dis();
-
-	msr.hi = (PCI_MMIO_BASE >> (32 - 8));
-	msr.lo = 0;
-	wrmsr(0xc0000101, msr);	//GS_Base Reg
+	msr.hi |= (PCI_MMIO_BASE >> (32));
 
+	wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
 #endif
 }
 
diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig
index be54fa7..fcc24ff 100644
--- a/src/mainboard/tyan/s2912_fam10/Kconfig
+++ b/src/mainboard/tyan/s2912_fam10/Kconfig
@@ -9,6 +9,7 @@  config BOARD_SPECIFIC_OPTIONS # dummy
 	select SUPERIO_WINBOND_W83627HF
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
+	select HAVE_MAINBOARD_RESOURCES
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select CACHE_AS_RAM
@@ -107,4 +108,8 @@  config HEAP_SIZE
 	hex
 	default 0xc0000
 
+config MMCONF_SUPPORT_DEFAULT
+       bool
+       default y
+
 endif # BOARD_TYAN_S2912_FAM10
diff --git a/src/mainboard/tyan/s2912_fam10/mainboard.c b/src/mainboard/tyan/s2912_fam10/mainboard.c
index ca78d96..2e44461 100644
--- a/src/mainboard/tyan/s2912_fam10/mainboard.c
+++ b/src/mainboard/tyan/s2912_fam10/mainboard.c
@@ -24,6 +24,7 @@ 
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <boot/tables.h>
 #include "hda_verb.h"
 #include "chip.h"
 
@@ -38,6 +39,11 @@  static void mainboard_enable(device_t dev)
 	verb_setup();
 }
 
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	return add_northbridge_resources(mem);
+}
+
 struct chip_operations mainboard_ops = {
 	CHIP_NAME("Tyan S2912 Mainboard (Family 10)")
 	.enable_dev = mainboard_enable,
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index 102753e..a3a3972 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -54,6 +54,21 @@  config HW_MEM_HOLE_SIZE_AUTO_INC
 	default n
 	depends on NORTHBRIDGE_AMD_AMDFAM10
 
+config MMCONF_SUPPORT
+	bool
+	default y
+	depends on NORTHBRIDGE_AMD_AMDFAM10
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xe0000000
+	depends on NORTHBRIDGE_AMD_AMDFAM10
+
+config MMCONF_BUS_NUMBER
+	int
+	default 256
+	depends on NORTHBRIDGE_AMD_AMDFAM10
+
 config BOOTBLOCK_NORTHBRIDGE_INIT
         string
         default "northbridge/amd/amdfam10/bootblock.c"
diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c
index b1c21f2..58f2cdd 100644
--- a/src/northbridge/amd/amdfam10/early_ht.c
+++ b/src/northbridge/amd/amdfam10/early_ht.c
@@ -129,7 +129,7 @@  static void enumerate_ht_chain(void)
 						PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
 
 					do {
-						ctrl = pci_read_config16(devx, pos + ctrl_off);
+						ctrl = pci_io_read_config16(devx, pos + ctrl_off);
 						/* Is this the end of the hypertransport chain? */
 						if (ctrl & (1 << 6)) {
 							goto out;
@@ -144,8 +144,8 @@  static void enumerate_ht_chain(void)
 							 * if its transient
 							 */
 							ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
-							pci_write_config16(devx, pos + ctrl_off, ctrl);
-							ctrl = pci_read_config16(devx, pos + ctrl_off);
+							pci_io_write_config16(devx, pos + ctrl_off, ctrl);
+							ctrl = pci_io_read_config16(devx, pos + ctrl_off);
 							if (ctrl & ((1 << 4) | (1 << 8))) {
 								// can not clear the error
 								break;
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index d8d1aa2..5795945 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -28,6 +28,7 @@ 
 #include <string.h>
 #include <bitops.h>
 #include <cpu/cpu.h>
+#include <boot/tables.h>
 
 #include <cpu/x86/lapic.h>
 
@@ -1149,6 +1150,17 @@  static struct device_operations pci_domain_ops = {
 #endif
 };
 
+int add_northbridge_resources(struct lb_memory *mem)
+{
+#if CONFIG_MMCONF_SUPPORT
+	printk(BIOS_DEBUG, "Adding MMCONF memory area\n");
+	lb_add_memory_range(mem, LB_MEM_RESERVED,
+			    CONFIG_MMCONF_BASE_ADDRESS,
+			    CONFIG_MMCONF_BUS_NUMBER * 4096*256);
+#endif
+	return 0;
+}
+
 static void sysconf_init(device_t dev) // first node
 {
 	sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
@@ -1440,9 +1452,28 @@  static void cpu_bus_noop(device_t dev)
 {
 }
 
+static void cpu_bus_read_resources(device_t dev)
+{
+#if CONFIG_MMCONF_SUPPORT
+	struct resource *resource = new_resource(dev, 0xc0010058);
+	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
+	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
+#endif
+}
+
+static void cpu_bus_set_resources(device_t dev)
+{
+	struct resource *resource = find_resource(dev, 0xc0010058);
+	if (resource) {
+		report_resource_stored(dev, resource, " <mmconfig>");
+	}
+	pci_dev_set_resources(dev);
+}
+
 static struct device_operations cpu_bus_ops = {
-	.read_resources	  = cpu_bus_noop,
-	.set_resources	  = cpu_bus_noop,
+	.read_resources	  = cpu_bus_read_resources,
+	.set_resources	  = cpu_bus_set_resources,
 	.enable_resources = cpu_bus_noop,
 	.init		  = cpu_bus_init,
 	.scan_bus	  = cpu_bus_scan,
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index afeb4e9..3693891 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -1970,7 +1970,7 @@  static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
 				reg  = 0x40 + (q << 2) + reg_off;  /* Base[q] reg.*/
 				val = Get_NB32(dev, reg);
 				if (!(val & 3)) {	/* (CSEnable|Spare==1)bank is enabled already? */
-					reg = 0x60 + (q << 1) + reg_off; /*Mask[q] reg.*/
+					reg = 0x60 + ((q << 1) & 0xc) + reg_off; /*Mask[q] reg.*/
 					val = Get_NB32(dev, reg);
 					val >>= 19;
 					val++;
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
index fb84f5a..e01630d 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
@@ -267,8 +267,13 @@  static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn
 	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
 	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
 	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
-
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
+	/* The following operation hangs when performed via MMCFG:
+	     pci_read_config32(romcc): 00010000:0078: 20040000
+	     setup_resource_map_x_offset: 10000, 78: 20040000
+	     pci_write_config32(romcc): 00010000:0078: 19040000
+	     (hang)
+	   Response missing? */
+	/* RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, */
 
 #if MCP55_USE_AZA == 1
 	RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,