===================================================================
@@ -20,6 +20,7 @@
* to the bus below.
*/
#define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */
+#define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the Coreboot table */
#define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */
#define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */
#define IORESOURCE_FIXED 0x80000000 /* An IO resource the allocator must not change */
===================================================================
@@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_HARD_RESET
select HAVE_ACPI_RESUME
- select HAVE_MAINBOARD_RESOURCES
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
select BOARD_ROMSIZE_KB_1024
===================================================================
@@ -20,20 +20,13 @@
#include <types.h>
#include <device/device.h>
#include <console/console.h>
-#include <boot/tables.h>
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>
#include <arch/io.h>
-#include <arch/coreboot_tables.h>
#include "chip.h"
-int add_mainboard_resources(struct lb_memory *mem)
-{
- return add_northbridge_resources(mem);
-}
-
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
static int int15_handler(void)
{
===================================================================
@@ -70,20 +70,26 @@ static int get_pcie_bar(u32 *base, u32 *
/* IDG memory */
uint64_t uma_memory_base=0, uma_memory_size=0;
-int add_northbridge_resources(struct lb_memory *mem)
+static void add_fixed_resources(struct device *dev, int index)
{
+ struct resource *resource;
u32 pcie_config_base, pcie_config_size;
printk(BIOS_DEBUG, "Adding UMA memory area\n");
- lb_add_memory_range(mem, LB_MEM_RESERVED,
- uma_memory_base, uma_memory_size);
-
- printk(BIOS_DEBUG, "Adding PCIe config bar\n");
- get_pcie_bar(&pcie_config_base, &pcie_config_size);
- lb_add_memory_range(mem, LB_MEM_RESERVED,
- pcie_config_base, pcie_config_size);
+ resource = new_resource(dev, index);
+ resource->base = (resource_t) uma_memory_base;
+ resource->size = (resource_t) uma_memory_size;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
- return 0;
+ if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
+ printk(BIOS_DEBUG, "Adding PCIe config bar\n");
+ resource = new_resource(dev, index+1);
+ resource->base = (resource_t) pcie_config_base;
+ resource->size = (resource_t) pcie_config_size;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+ }
}
static void ram_resource(device_t dev, unsigned long index, unsigned long basek,
@@ -208,6 +214,8 @@ static void pci_domain_set_resources(dev
ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
}
+ add_fixed_resources(dev, 6);
+
assign_resources(dev->link_list);
#if CONFIG_WRITE_HIGH_TABLES==1
===================================================================
@@ -488,6 +488,21 @@ static struct lb_memory *build_lb_mem(st
return mem;
}
+static void lb_add_rsvd_range(void *gp, struct device *dev, struct resource *res)
+{
+ struct lb_memory *mem = gp;
+ lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size);
+}
+
+static void *add_lb_reserved(struct lb_memory *mem)
+{
+ /* Add reserved ranges */
+ search_global_resources(
+ IORESOURCE_MEM | IORESOURCE_RESERVE, IORESOURCE_MEM | IORESOURCE_RESERVE,
+ lb_add_rsvd_range, mem);
+ return mem;
+}
+
#if CONFIG_WRITE_HIGH_TABLES == 1
extern uint64_t high_tables_base, high_tables_size;
#endif
@@ -562,6 +577,9 @@ unsigned long write_coreboot_table(
high_tables_base, high_tables_size);
#endif
+ /* Add reserved regions */
+ add_lb_reserved(mem);
+
#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
add_mainboard_resources(mem);
#endif
Here's a first stab at what I mean. It compiles, but I don't have the board to test. Signed-off-by: Myles Watson <mylesgw@gmail.com> Patrick and Stefan, Could you comment. I'd like it even better if the resources were added earlier, but I didn't want to change too much at once. Thanks, Myles