Patchwork AMD MMCONF Support

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Submitter Arne Georg Gleditsch
Date 2010-09-09 07:22:17
Message ID <87hbhztm8m.fsf@taniquetil.gledits.ch>
Download mbox | patch
Permalink /patch/1893/
State Accepted
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Comments

Arne Georg Gleditsch - 2010-09-09 07:22:17
Myles Watson <mylesgw@gmail.com> writes:
> Here's a first stab at what I mean.  It compiles, but I don't have the
> board to test.

Ok, so building on that, here's an updated version of the first patch.
The resource is still fixed, but the gratuitous call through
add_mainboard_resource is gone and the coreboot table manipulation is
removed from the northbridge code.
Arne Georg Gleditsch - 2010-09-09 07:31:32
Arne Georg Gleditsch <arne.gleditsch@numascale.com> writes:
> Ok, so building on that, here's an updated version of the first patch.
> The resource is still fixed, but the gratuitous call through
> add_mainboard_resource is gone and the coreboot table manipulation is
> removed from the northbridge code.

For the record, this version is also

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Myles Watson - 2010-09-09 14:56:14
On Thu, Sep 9, 2010 at 1:31 AM, Arne Georg Gleditsch
<arne.gleditsch@numascale.com> wrote:
> Arne Georg Gleditsch <arne.gleditsch@numascale.com> writes:
>> Ok, so building on that, here's an updated version of the first patch.
>> The resource is still fixed, but the gratuitous call through
>> add_mainboard_resource is gone and the coreboot table manipulation is
>> removed from the northbridge code.
>
> For the record, this version is also
>
> Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

Rev 5795.
Rev 5796.

I split it into two to make it easier to understand.  I almost split
it again so that your bug fixes were separate from the board-specific
code.

Thanks,
Myles
Myles Watson - 2010-09-09 15:23:24
-
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
+	/* The following operation hangs when performed via MMCFG:
+	     pci_read_config32(romcc): 00010000:0078: 20040000
+	     setup_resource_map_x_offset: 10000, 78: 20040000
+	     pci_write_config32(romcc): 00010000:0078: 19040000
+	     (hang)
+	   Response missing? */
+	/* RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, */

I forgot to ask if you'd tried setting the SyncOnWdError bit (20) in
function 3, register 0x44.  That could help further debug this
problem.  For me it caused a reboot instead of a hang when there was a
response missing.  Bit 21 could also be helpful.

Since we don't have the chipset documentation, it makes me a little
worried to leave out one of the settings.  Maybe we could use non
MMCONF writes for that setting.

Thanks,
Myles
Arne Georg Gleditsch - 2010-09-10 09:17:21
Myles Watson <mylesgw@gmail.com> writes:
> -
> -	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
> +	/* The following operation hangs when performed via MMCFG:
> +	     pci_read_config32(romcc): 00010000:0078: 20040000
> +	     setup_resource_map_x_offset: 10000, 78: 20040000
> +	     pci_write_config32(romcc): 00010000:0078: 19040000
> +	     (hang)
> +	   Response missing? */
> +	/* RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, */
>
> I forgot to ask if you'd tried setting the SyncOnWdError bit (20) in
> function 3, register 0x44.  That could help further debug this
> problem.  For me it caused a reboot instead of a hang when there was a
> response missing.  Bit 21 could also be helpful.

I can have a look.  I won't get a chance until Monday, though.

> Since we don't have the chipset documentation, it makes me a little
> worried to leave out one of the settings.  Maybe we could use non
> MMCONF writes for that setting.

We could fall back to that, if we want to keep it.  FWIW, Ed Swierk had
some input on the semantics of this register the last time this came up:
http://thread.gmane.org/gmane.linux.bios/57708/focus=59900
Arne Georg Gleditsch - 2010-09-13 12:36:36
Arne Georg Gleditsch <arne.gleditsch@numascale.com> writes:
>> -	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
>> +	/* The following operation hangs when performed via MMCFG:
>> +	     pci_read_config32(romcc): 00010000:0078: 20040000
>> +	     setup_resource_map_x_offset: 10000, 78: 20040000
>> +	     pci_write_config32(romcc): 00010000:0078: 19040000
>> +	     (hang)
>> +	   Response missing? */
>> +	/* RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, */
>>
>> I forgot to ask if you'd tried setting the SyncOnWdError bit (20) in
>> function 3, register 0x44.  That could help further debug this
>> problem.  For me it caused a reboot instead of a hang when there was a
>> response missing.  Bit 21 could also be helpful.
>
> I can have a look.  I won't get a chance until Monday, though.

Ah, I've just stumbled across something.
src/mainboard/tyan/s2912_fam10/romstage.c:sio_setup does: 

  byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
  byte |= 0x20;
  pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);

It appears that the offending RES_PCI_IO line is not so much hanging the
system as disabling the serial console.  Furthermore, the reason this
does not happen when using pio-based config space accesses seems to be
that several functions, for instance precisely sio_setup, are using
pci_read/write_config before init_cpus has run and thus begore the
MMCONF BAR is set up.  This means these accesses are effectively ignored
when MMCONF is enabled.  Some of these are apparently required for the
RES_PCI_IO in question to be set without affecting the serial output.

Rather than hunt around and try to change all config accesses that might
run before init_cpus to explicit pio-accesses, I've moved the BAR init
to run as early as possible, in cache_as_ram.  With this change, I can
re-insert the RES_PCI_IO wihtout ill effects.

> We could fall back to that, if we want to keep it.  FWIW, Ed Swierk had
> some input on the semantics of this register the last time this came up:
> http://thread.gmane.org/gmane.linux.bios/57708/focus=59900

(The correct link to Ed's post is
http://thread.gmane.org/gmane.linux.bios/57708/focus=58810)

Patch

diff --git a/src/arch/i386/boot/coreboot_table.c b/src/arch/i386/boot/coreboot_table.c
index f44e3dd..03bb293 100644
--- a/src/arch/i386/boot/coreboot_table.c
+++ b/src/arch/i386/boot/coreboot_table.c
@@ -488,6 +488,21 @@  static struct lb_memory *build_lb_mem(struct lb_header *head)
 	return mem;
 }
 
+static void lb_add_rsvd_range(void *gp, struct device *dev, struct resource *res)
+{
+	struct lb_memory *mem = gp;
+	lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size);
+}
+
+static void *add_lb_reserved(struct lb_memory *mem)
+{
+	/* Add reserved ranges */
+	search_global_resources(
+		IORESOURCE_MEM | IORESOURCE_RESERVE, IORESOURCE_MEM | IORESOURCE_RESERVE,
+		lb_add_rsvd_range, mem);
+	return mem;
+}
+
 #if CONFIG_WRITE_HIGH_TABLES == 1
 extern uint64_t high_tables_base, high_tables_size;
 #endif
@@ -562,6 +577,9 @@  unsigned long write_coreboot_table(
 		high_tables_base, high_tables_size);
 #endif
 
+	/* Add reserved regions */
+	add_lb_reserved(mem);
+
 #if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
 	add_mainboard_resources(mem);
 #endif
diff --git a/src/arch/i386/include/arch/mmio_conf.h b/src/arch/i386/include/arch/mmio_conf.h
index df91cb5..08962f0 100644
--- a/src/arch/i386/include/arch/mmio_conf.h
+++ b/src/arch/i386/include/arch/mmio_conf.h
@@ -2,13 +2,13 @@ 
 #define ARCH_MMIO_H 1
 
 
-//extended read, GS is already set
+// Extended read, constrain to use registers as mandated by AMD MMCONFIG mechanism.
 
 static inline __attribute__((always_inline)) uint8_t read8x(uint32_t addr)
 {
 	uint8_t value;
         __asm__ volatile (
-                "movb %%gs:(%1), %0\n\t"
+                "movb (%1), %%al\n\t"
                 :"=a"(value): "b" (addr)
         );
         return value;
@@ -18,7 +18,7 @@  static inline __attribute__((always_inline)) uint16_t read16x(uint32_t addr)
 {
         uint16_t value;
         __asm__ volatile (
-                "movw %%gs:(%1), %0\n\t"
+                "movw (%1), %%ax\n\t"
                 :"=a"(value): "b" (addr)
         );
 
@@ -30,7 +30,7 @@  static inline __attribute__((always_inline)) uint32_t read32x(uint32_t addr)
 {
         uint32_t value;
         __asm__ volatile (
-                "movl %%gs:(%1), %0\n\t"
+                "movl (%1), %%eax\n\t"
                 :"=a"(value): "b" (addr)
         );
 
@@ -41,7 +41,7 @@  static inline __attribute__((always_inline)) uint32_t read32x(uint32_t addr)
 static inline __attribute__((always_inline)) void write8x(uint32_t addr, uint8_t value)
 {
         __asm__ volatile (
-                "movb %1, %%gs:(%0)\n\t"
+                "movb %%al, (%0)\n\t"
                 :: "b" (addr), "a" (value)
         );
 
@@ -50,7 +50,7 @@  static inline __attribute__((always_inline)) void write8x(uint32_t addr, uint8_t
 static inline __attribute__((always_inline)) void write16x(uint32_t addr, uint16_t value)
 {
         __asm__ volatile (
-                "movw %1, %%gs:(%0)\n\t"
+                "movw %%ax, (%0)\n\t"
                 :: "b" (addr), "a" (value)
         );
 
@@ -59,7 +59,7 @@  static inline __attribute__((always_inline)) void write16x(uint32_t addr, uint16
 static inline __attribute__((always_inline)) void write32x(uint32_t addr, uint32_t value)
 {
         __asm__ volatile (
-                "movl %1, %%gs:(%0)\n\t"
+                "movl %%eax, (%0)\n\t"
                 :: "b" (addr), "a" (value)
         );
 }
diff --git a/src/arch/i386/include/arch/romcc_io.h b/src/arch/i386/include/arch/romcc_io.h
index 6bc7dfc..79ea265 100644
--- a/src/arch/i386/include/arch/romcc_io.h
+++ b/src/arch/i386/include/arch/romcc_io.h
@@ -107,7 +107,7 @@  static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(devic
 static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
 {
         unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1);
         return read16x(addr);
 }
 #endif
@@ -138,7 +138,7 @@  static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(devic
 static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
 {
         unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3);
         return read32x(addr);
 }
 #endif
@@ -199,7 +199,7 @@  static inline __attribute__((always_inline)) void pci_io_write_config16(device_t
 static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value)
 {
         unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1);
         write16x(addr, value);
 }
 #endif
@@ -230,7 +230,7 @@  static inline __attribute__((always_inline)) void pci_io_write_config32(device_t
 static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value)
 {
         unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3);
         write32x(addr, value);
 }
 #endif
diff --git a/src/arch/i386/lib/pci_ops_mmconf.c b/src/arch/i386/lib/pci_ops_mmconf.c
index a605708..7d8fb32 100644
--- a/src/arch/i386/lib/pci_ops_mmconf.c
+++ b/src/arch/i386/lib/pci_ops_mmconf.c
@@ -27,12 +27,12 @@  static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, int
 
 static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, int where)
 {
-                return (read16x(PCI_MMIO_ADDR(bus, devfn, where)));
+                return (read16x(PCI_MMIO_ADDR(bus, devfn, where) & ~1));
 }
 
 static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, int where)
 {
-                return (read32x(PCI_MMIO_ADDR(bus, devfn, where)));
+                return (read32x(PCI_MMIO_ADDR(bus, devfn, where) & ~3));
 }
 
 static void  pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value)
@@ -42,12 +42,12 @@  static void  pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, int
 
 static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value)
 {
-                write8x(PCI_MMIO_ADDR(bus, devfn, where), value);
+                write16x(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value);
 }
 
 static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value)
 {
-                write8x(PCI_MMIO_ADDR(bus, devfn, where), value);
+                write32x(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value);
 }
 
 
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index a499f5f..11dea97 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -57,32 +57,28 @@  static void set_EnableCf8ExtCfg(void)
 static void set_EnableCf8ExtCfg(void) { }
 #endif
 
-/*[39:8] */
-#define PCI_MMIO_BASE 0xfe000000
-/* because we will use gs to store hi, so need to make sure lo can start
-   from 0, So PCI_MMIO_BASE & 0x00ffffff should be equal to 0*/
+
+#define _ULLx(x) x ## ULL
+#define _ULL(x) _ULLx(x)
+
+/*[63:0] */
+#define PCI_MMIO_BASE _ULL(CONFIG_MMCONF_BASE_ADDRESS)
 
 static void set_pci_mmio_conf_reg(void)
 {
 #if CONFIG_MMCONF_SUPPORT
+#  if PCI_MMIO_BASE > 0xffffffff
+#    error CONFIG_MMCONF_BASE_ADDRESS must currently fit in 32 bits!
+#  endif
 	msr_t msr;
 	msr = rdmsr(0xc0010058);
 	msr.lo &= ~(0xfff00000 | (0xf << 2));
-	// 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space
-	msr.lo |= ((8 + CONFIG_PCI_BUS_SEGN_BITS) << 2) | (1 << 0);
+	// 256 buses, one segment. Total 256M address space.
+	msr.lo |= (PCI_MMIO_BASE & 0xfff00000) | (8 << 2) | (1 << 0);
 	msr.hi &= ~(0x0000ffff);
-	msr.hi |= (PCI_MMIO_BASE >> (32 - 8));
-	wrmsr(0xc0010058, msr);	// MMIO Config Base Address Reg
-
-	//mtrr for that range?
-	// set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
-
-	set_wrap32dis();
-
-	msr.hi = (PCI_MMIO_BASE >> (32 - 8));
-	msr.lo = 0;
-	wrmsr(0xc0000101, msr);	//GS_Base Reg
+	msr.hi |= (PCI_MMIO_BASE >> (32));
 
+	wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
 #endif
 }
 
diff --git a/src/include/device/resource.h b/src/include/device/resource.h
index 49e2185..b2e3e99 100644
--- a/src/include/device/resource.h
+++ b/src/include/device/resource.h
@@ -20,6 +20,7 @@ 
 						 * to the bus below.
 						 */
 #define IORESOURCE_BRIDGE	0x00080000	/* The IO resource has a bus below it. */
+#define IORESOURCE_RESERVE	0x10000000	/* The resource needs to be reserved in the Coreboot table */
 #define IORESOURCE_STORED	0x20000000	/* The IO resource assignment has been stored in the device */
 #define IORESOURCE_ASSIGNED	0x40000000	/* An IO resource that has been assigned a value */
 #define IORESOURCE_FIXED	0x80000000	/* An IO resource the allocator must not change */
diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig
index be54fa7..e00408b 100644
--- a/src/mainboard/tyan/s2912_fam10/Kconfig
+++ b/src/mainboard/tyan/s2912_fam10/Kconfig
@@ -18,6 +18,7 @@  config BOARD_SPECIFIC_OPTIONS # dummy
 	select ENABLE_APIC_EXT_ID
 	select AMDMCT
 	select TINY_BOOTBLOCK
+	select MMCONF_SUPPORT_DEFAULT
 
 config MAINBOARD_DIR
 	string
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index 102753e..5ba0fa9 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -23,6 +23,7 @@  config NORTHBRIDGE_AMD_AMDFAM10
 	select HAVE_DEBUG_SMBUS
 	select HYPERTRANSPORT_PLUGIN_SUPPORT
 	select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
+	select MMCONF_SUPPORT
 
 config AGP_APERTURE_SIZE
 	hex
@@ -54,6 +55,16 @@  config HW_MEM_HOLE_SIZE_AUTO_INC
 	default n
 	depends on NORTHBRIDGE_AMD_AMDFAM10
 
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xe0000000
+	depends on NORTHBRIDGE_AMD_AMDFAM10
+
+config MMCONF_BUS_NUMBER
+	int
+	default 256
+	depends on NORTHBRIDGE_AMD_AMDFAM10
+
 config BOOTBLOCK_NORTHBRIDGE_INIT
         string
         default "northbridge/amd/amdfam10/bootblock.c"
diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c
index b1c21f2..58f2cdd 100644
--- a/src/northbridge/amd/amdfam10/early_ht.c
+++ b/src/northbridge/amd/amdfam10/early_ht.c
@@ -129,7 +129,7 @@  static void enumerate_ht_chain(void)
 						PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
 
 					do {
-						ctrl = pci_read_config16(devx, pos + ctrl_off);
+						ctrl = pci_io_read_config16(devx, pos + ctrl_off);
 						/* Is this the end of the hypertransport chain? */
 						if (ctrl & (1 << 6)) {
 							goto out;
@@ -144,8 +144,8 @@  static void enumerate_ht_chain(void)
 							 * if its transient
 							 */
 							ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
-							pci_write_config16(devx, pos + ctrl_off, ctrl);
-							ctrl = pci_read_config16(devx, pos + ctrl_off);
+							pci_io_write_config16(devx, pos + ctrl_off, ctrl);
+							ctrl = pci_io_read_config16(devx, pos + ctrl_off);
 							if (ctrl & ((1 << 4) | (1 << 8))) {
 								// can not clear the error
 								break;
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index d8d1aa2..765242a 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -1440,9 +1440,29 @@  static void cpu_bus_noop(device_t dev)
 {
 }
 
+static void cpu_bus_read_resources(device_t dev)
+{
+#if CONFIG_MMCONF_SUPPORT
+	struct resource *resource = new_resource(dev, 0xc0010058);
+	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
+	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | 
+		IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
+#endif
+}
+
+static void cpu_bus_set_resources(device_t dev)
+{
+	struct resource *resource = find_resource(dev, 0xc0010058);
+	if (resource) {
+		report_resource_stored(dev, resource, " <mmconfig>");
+	}
+	pci_dev_set_resources(dev);
+}
+
 static struct device_operations cpu_bus_ops = {
-	.read_resources	  = cpu_bus_noop,
-	.set_resources	  = cpu_bus_noop,
+	.read_resources	  = cpu_bus_read_resources,
+	.set_resources	  = cpu_bus_set_resources,
 	.enable_resources = cpu_bus_noop,
 	.init		  = cpu_bus_init,
 	.scan_bus	  = cpu_bus_scan,
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index afeb4e9..3693891 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -1970,7 +1970,7 @@  static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
 				reg  = 0x40 + (q << 2) + reg_off;  /* Base[q] reg.*/
 				val = Get_NB32(dev, reg);
 				if (!(val & 3)) {	/* (CSEnable|Spare==1)bank is enabled already? */
-					reg = 0x60 + (q << 1) + reg_off; /*Mask[q] reg.*/
+					reg = 0x60 + ((q << 1) & 0xc) + reg_off; /*Mask[q] reg.*/
 					val = Get_NB32(dev, reg);
 					val >>= 19;
 					val++;
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
index fb84f5a..e01630d 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
@@ -267,8 +267,13 @@  static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn
 	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
 	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
 	RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
-
-	RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
+	/* The following operation hangs when performed via MMCFG:
+	     pci_read_config32(romcc): 00010000:0078: 20040000
+	     setup_resource_map_x_offset: 10000, 78: 20040000
+	     pci_write_config32(romcc): 00010000:0078: 19040000
+	     (hang)
+	   Response missing? */
+	/* RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, */
 
 #if MCP55_USE_AZA == 1
 	RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,