Patchwork AMD cache setup is broken

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Submitter Arne Georg Gleditsch
Date 2010-09-09 09:16:51
Message ID <87sk1js2d8.fsf@taniquetil.gledits.ch>
Download mbox | patch
Permalink /patch/1895/
State Accepted
Commit r5791
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Comments

Arne Georg Gleditsch - 2010-09-09 09:16:51
Arne Georg Gleditsch <arne.gleditsch@numascale.com> writes:
> I can confirm that this removes the earlier observed delays for me.
> Obviously, this is AMD-specific code that needs to be hooked in in a
> proper manner, but this definately seems to be the culprit.

Apparently, it's not crucial to clear this at the exact moment we switch
to using ram, so something like the appended is perhaps more
appropriate.  Confirmed to work on hw.

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Patrick Georgi - 2010-09-09 09:56:39
Am 09.09.2010 11:16, schrieb Arne Georg Gleditsch:
> Apparently, it's not crucial to clear this at the exact moment we switch
> to using ram, so something like the appended is perhaps more
> appropriate.  Confirmed to work on hw.
> 
> Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>

and in as r5791


Thanks,
Patrick
Arne Georg Gleditsch - 2010-09-09 09:58:08
Arne Georg Gleditsch <arne.gleditsch@numascale.com> writes:
> +	/* Clear ClLinesToNbDis */
> +	msr = rdmsr(BU_CFG2_MSR);
> +	msr.lo &= ~(1 << 15);
> +	wrmsr(BU_CFG2_MSR, msr);

On an slightly unrelated note; do we want to clear bit 35 here as well?
At the moment, this is only done for the BSP, causing the MSR settings
to be inconsistent after boot.  I see that errata 343 indicates that
this should be cleared after CAR is disabled, so it might not matter all
that much for the APs...
Scott - 2010-09-09 15:02:58
]-----Original Message-----
]From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Arne Georg Gleditsch
]Sent: Thursday, September 09, 2010 04:58 AM
]To: Scott Duplichan
]Cc: 'Marc Jones'; coreboot@coreboot.org
]Subject: Re: [coreboot] AMD cache setup is broken
]
]Arne Georg Gleditsch <arne.gleditsch@numascale.com> writes:
]> +	/* Clear ClLinesToNbDis */
]> +	msr = rdmsr(BU_CFG2_MSR);
]> +	msr.lo &= ~(1 << 15);
]> +	wrmsr(BU_CFG2_MSR, msr);
]
]On an slightly unrelated note; do we want to clear bit 35 here as well?
]At the moment, this is only done for the BSP, causing the MSR settings
]to be inconsistent after boot.  I see that errata 343 indicates that
]this should be cleared after CAR is disabled, so it might not matter all
]that much for the APs...

I think it would be best to clear bit 35 of msr c001_102a in the AP
cores as well as the BSP core. Otherwise, the OS might see AP cores
having slightly lower performance than the BSP core. This bit affects
family 10h revC and newer (45 nm).

Thanks,
Scott

]
]-- 
]							Arne.

Patch

diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 992c957..6f61fc3 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -113,6 +113,11 @@  static void model_10xxx_init(device_t dev)
 	msr.hi &= ~(1 << (46 - 32));
 	wrmsr(NB_CFG_MSR, msr);
 
+	/* Clear ClLinesToNbDis */
+	msr = rdmsr(BU_CFG2_MSR);
+	msr.lo &= ~(1 << 15);
+	wrmsr(BU_CFG2_MSR, msr);
+
 	/* Write protect SMM space with SMMLOCK. */
 	msr = rdmsr(HWCR_MSR);
 	msr.lo |= (1 << 0);
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 3693891..400071d 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -3189,7 +3189,7 @@  static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
 	print_t("\tmct_FinalMCT_D: Clr Cl, Wb\n");
 
 
-	mct_ClrClToNB_D(pMCTstat, pDCTstat);
+	/* ClrClToNB_D postponed til we're done executing from ROM */
 	mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat);
 }