| Submitter | Arne Georg Gleditsch |
|---|---|
| Date | 2010-09-09 10:06:30 |
| Message ID | <87k4mvs02h.fsf@taniquetil.gledits.ch> |
| Download | mbox | patch |
| Permalink | /patch/1896/ |
| State | Accepted |
| Headers | show |
Comments
Am 09.09.2010 12:06, schrieb Arne Georg Gleditsch: > I guess we want to do this in the DDR3 path as, well. Patch appended to > do so, as well as fix a minor typo in the last one. > > Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> r5792 Thanks, Patrick
On Thu, Sep 9, 2010 at 4:35 AM, Patrick Georgi <patrick@georgi-clan.de> wrote: > Am 09.09.2010 12:06, schrieb Arne Georg Gleditsch: >> I guess we want to do this in the DDR3 path as, well. Patch appended to >> do so, as well as fix a minor typo in the last one. >> >> Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com> > Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> > > r5792 Thanks for doing this. I got sucked into other issues yesterday.... Marc
So, after all this, I think we still need the lzma change that Arne proposed. I have found that the videobios decompress is still slow, which is after the rom caching is disabled. Marc
Marc Jones <marcj303@gmail.com> writes: > So, after all this, I think we still need the lzma change that Arne > proposed. I have found that the videobios decompress is still slow, > which is after the rom caching is disabled. I thought the decompress itself needed to run from ROM for us to see this. What kind of video bios is this; is it embedded in the coreboot image or is it hosted on an external video card? I have a vague recollection of there being a facility or hook that allowed option roms to copy themselves from ROM to RAM, could that be involved here?
On Sat, Sep 11, 2010 at 5:05 AM, Arne Georg Gleditsch <arne.gleditsch@numascale.com> wrote: > Marc Jones <marcj303@gmail.com> writes: >> So, after all this, I think we still need the lzma change that Arne >> proposed. I have found that the videobios decompress is still slow, >> which is after the rom caching is disabled. > > I thought the decompress itself needed to run from ROM for us to see > this. What kind of video bios is this; is it embedded in the coreboot > image or is it hosted on an external video card? I have a vague > recollection of there being a facility or hook that allowed option roms > to copy themselves from ROM to RAM, could that be involved here? This is a lzma compressed rom embeeded in the coreboot image. Marc
Marc Jones <marcj303@gmail.com> writes: >> I thought the decompress itself needed to run from ROM for us to see >> this. What kind of video bios is this; is it embedded in the coreboot >> image or is it hosted on an external video card? I have a vague >> recollection of there being a facility or hook that allowed option roms >> to copy themselves from ROM to RAM, could that be involved here? > > This is a lzma compressed rom embeeded in the coreboot image. Then I don't think I quite understand what happens... The ramstage contains its own copy of ulzma, does it not? Does the copy-to-stack approach actually help in your case? How about delaying the clear ClLinesToNbDis-operation?
Patch
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 400071d..4233705 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -3189,7 +3189,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, print_t("\tmct_FinalMCT_D: Clr Cl, Wb\n"); - /* ClrClToNB_D postponed til we're done executing from ROM */ + /* ClrClToNB_D postponed until we're done executing from ROM */ mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 6eea6e4..b6782bc 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2873,7 +2873,7 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat, static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { - mct_ClrClToNB_D(pMCTstat, pDCTstat); + /* ClrClToNB_D postponed until we're done executing from ROM */ mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat); }