Patchwork [RFC] More debugging for SB600/SB700 SPI

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Submitter Carl-Daniel Hailfinger
Date 2009-07-11 13:29:49
Message ID <4A5893CD.5020509@gmx.net>
Download mbox | patch
Permalink /patch/19/
State Superseded
Headers show

Comments

Carl-Daniel Hailfinger - 2009-07-11 13:29:49
More debugging for SB600/SB700 SPI.
Some of this should be conditional on SB700. Anyway, it should be
harmless on SB600.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Patch

Index: flashrom-spi_sb600_sb700_debug/chipset_enable.c
===================================================================
--- flashrom-spi_sb600_sb700_debug/chipset_enable.c	(Revision 645)
+++ flashrom-spi_sb600_sb700_debug/chipset_enable.c	(Arbeitskopie)
@@ -692,7 +692,9 @@ 
 
 	/* Read SPI_BaseAddr */
 	tmp = pci_read_long(dev, 0xa0);
-	tmp &= 0xfffffff0;	/* remove low 4 bits (reserved) */
+	printf_debug("AltSpiCSEnable=%i, SpiRomEnable=%i, AbortEnable=%i\n",
+			tmp & 0x1, (tmp & 0x2) >> 1, (tmp & 0x4) >> 2);
+	tmp &= 0xffffffe0;	/* remove bits 4-0 (reserved) */
 	printf_debug("SPI base address is at 0x%x\n", tmp);
 
 	/* If the BAR has address 0, it is unlikely SPI is used. */
@@ -704,6 +706,13 @@ 
 	/* The low bits of the SPI base address are used as offset into the mapped page */
 	sb600_spibar += tmp & 0xfff;
 
+	tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2;
+	printf_debug("PrefetchEnSPIFromIMC=%i, ", tmp);
+
+	tmp = pci_read_byte(dev, 0xbb);
+	printf_debug("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n",
+			tmp & 0x1, (tmp & 0x20) >> 5);
+
 	/* Look for the SMBus device. */
 	smbus_dev = pci_dev_find(0x1002, 0x4385);
 
Index: flashrom-spi_sb600_sb700_debug/sb600spi.c
===================================================================
--- flashrom-spi_sb600_sb700_debug/sb600spi.c	(Revision 645)
+++ flashrom-spi_sb600_sb700_debug/sb600spi.c	(Arbeitskopie)
@@ -117,13 +117,13 @@ 
 
 	if (readcnt > 8) {
 		printf("%s, SB600 SPI controller can not receive %d bytes, "
-		       "which is limited with 8 bytes\n", __func__, readcnt);
+		       "it is limited to 8 bytes\n", __func__, readcnt);
 		return 1;
 	}
 
 	if (writecnt > 8) {
-		printf("%s, SB600 SPI controller can not sent %d bytes, "
-		       "which is limited with 8 bytes\n", __func__, writecnt);
+		printf("%s, SB600 SPI controller can not send %d bytes, "
+		       "it is limited to 8 bytes\n", __func__, writecnt);
 		return 1;
 	}
 
@@ -136,6 +136,7 @@ 
 	/* Send the write byte to FIFO. */
 	for (count = 0; count < writecnt; count++, writearr++) {
 		printf_debug(" [%x]", *writearr);
+		/* FIXME: Can we rely on auto-posting these writes or do we have to issue a read afterwards? */
 		mmio_writeb(*writearr, sb600_spibar + 0xC);
 	}
 	printf_debug("\n");
@@ -153,19 +154,28 @@ 
 	 * received byte. Here we just reset the FIFO pointer, skip the
 	 * writecnt, is there anyone who have anther method to replace it?
 	 */
+	printf_debug("The FIFO pointer before reset is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07);
 	reset_internal_fifo_pointer();
 
 	for (count = 0; count < writecnt; count++) {
-		cmd = mmio_readb(sb600_spibar + 0xC);	/* Skip the byte we send. */
+		cmd = mmio_readb(sb600_spibar + 0xC);	/* Skip the bytes we send. */
 		printf_debug("[ %2x]", cmd);
 	}
 
-	printf_debug("The FIFO pointer 6 is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07);
+	printf_debug("The FIFO pointer after skipping is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07);
 	for (count = 0; count < readcnt; count++, readarr++) {
 		*readarr = mmio_readb(sb600_spibar + 0xC);
 		printf_debug("[%02x]", *readarr);
 	}
 	printf_debug("\n");
 
+	printf_debug("The FIFO pointer after reading is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07);
+	printf_debug("Dumping everything that's left in the FIFO\n");
+	for (count = 0; count < 8; count++) {
+		cmd = mmio_readb(sb600_spibar + 0xC);
+		printf_debug("[ %2x]", cmd);
+	}
+	printf_debug("The FIFO pointer after dumping is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07);
+
 	return 0;
 }