Patchwork Add support for Asus M4A785-M, with build instructions

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Submitter Myles Watson
Date 2010-09-10 15:54:27
Message ID <AANLkTinp70HNwiORjGA8XNepnXis8vB73Vg37Er5kYPp@mail.gmail.com>
Download mbox | patch
Permalink /patch/1907/
State Superseded
Headers show

Comments

Myles Watson - 2010-09-10 15:54:27
>>  From your mainboard's Kconfig:
>>
>> +config DIMM_SUPPORT
>> +       hex
>> +       default 0x0004
>> +       depends on CPU_AMD_SOCKET_AM3
>>
>> This really worries me.  You shouldn't need to change the type of memory
>> on
>> the Socket.  I looked at your board online, and they suggest that your
>> board
>> supports socket AM2, AM2+, and AM3.  That seems like it breaks our model.
>>  I
>> thought AM2 was DDR2 and AM3 was DDR3.
>
> Sorry to break your design, but that was what I had to do to get the RAM
> working.
I wasn't offended.  I just want to improve the design if it's broken.

> I can confirm that I am using DDR2 memory and the CPU is this:
>
> http://products.amd.com/en-na/DesktopCPUDetail.aspx?id=615
Thanks.

>> In general, the fewer changes the better!
>
> I agree. The patches could be smaller and neater.
>
> However, I cannot hold on to this board for arbitrarily long, since I should
> put it to production use now that Coreboot is working.  I will see what I
> can do to reduce these patches further, if I just find a suitable slot of
> time.

I appreciate the work that you've done.  I've attached patches that
I've reduced a little more.  Would you test/review them?  If they
work, I'll commit them.

Signed-off-by: Myles Watson <mylesgw@gmail.com>

Thanks,
Myles
Juhana Helovuo - 2010-09-11 10:48:47
On Fri, 2010-09-10 at 09:54 -0600, Myles Watson wrote:

> I appreciate the work that you've done.  I've attached patches that
> I've reduced a little more.  Would you test/review them?  If they
> work, I'll commit them.
> 
> Signed-off-by: Myles Watson <mylesgw@gmail.com>


Thanks for your trouble of cleaning up.


I tried the patches you sent just now. Since Socket/DIMM type
configuration was changed in rev 5800, I tested these against rev 5799.

Patching and building is ok. Booting looks fine, Grub2 comes up and
loads Linux. However, Linux cannot find SATA controller, and because of
that, the booting fails. (Although Grub just loaded the kernel and
initrd from SATA.)

Linux gives the following complaints that I have not seen before:

[    1.620006] pci 0000:00:12.0: OHCI: BIOS handoff failed (BIOS bug?) ffffffff
[    2.424005] pci 0000:00:12.1: OHCI: BIOS handoff failed (BIOS bug?) ffffffff
[    2.431115] pci 0000:00:12.2: EHCI: unrecognized capability 02
[    3.236005] pci 0000:00:13.0: OHCI: BIOS handoff failed (BIOS bug?) ffffffff
[    4.040005] pci 0000:00:13.1: OHCI: BIOS handoff failed (BIOS bug?) ffffffff
[    4.047129] pci 0000:00:13.2: EHCI: unrecognized capability 02
[    4.852005] pci 0000:00:14.5: OHCI: BIOS handoff failed (BIOS bug?) ffffffff
...
[    6.524010] ahci 0000:00:11.0: controller reset failed (0xffffffff)
[    6.530976] ahci 0000:00:11.0: PCI INT A disabled
[    6.536129] ahci: probe of 0000:00:11.0 failed with error -5
[    6.542497] ehci_hcd 0000:00:13.2: PCI INT B -> GSI 19 (level, low) -> IRQ 19
[    6.550296] ehci_hcd 0000:00:13.2: EHCI Host Controller
[    6.556084] ehci_hcd 0000:00:13.2: new USB bus registered, assigned bus number 1
[    6.574836] ehci_hcd 0000:00:13.2: can't setup
[    6.579802] ehci_hcd 0000:00:13.2: USB bus 1 deregistered
[    6.585744] ehci_hcd 0000:00:13.2: PCI INT B disabled
[    6.591369] ehci_hcd 0000:00:13.2: init 0000:00:13.2 fail, -110
[    6.597905] ehci_hcd: probe of 0000:00:13.2 failed with error -110
[    6.608546] sd 1:0:0:0: [sda] 15621984 512-byte logical blocks: (7.99 GB/7.44 GiB)
[    6.613539] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    6.613588] ohci_hcd 0000:00:12.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[    6.613609] ohci_hcd 0000:00:12.0: OHCI Host Controller
[    6.613626] ohci_hcd 0000:00:12.0: new USB bus registered, assigned bus number 1
[    6.645506] sd 1:0:0:0: [sda] Write Protect is off
[    6.650743] sd 1:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't suppoA
[    6.660904]  sda: sda1 sda2 < sda5 >
[    6.666370] sd 1:0:0:0: [sda] Attached SCSI disk
[    6.676803] sr0: scsi3-mmc drive: 0x/48x cd/rw xa/form2 cdda tray
[    6.683415] Uniform CD-ROM driver Revision: 3.20
[    6.692578] sd 1:0:0:0: Attached scsi generic sg0 type 0
[    6.698631] sr 1:0:1:0: Attached scsi generic sg1 type 5
[   14.612006] ohci_hcd 0000:00:12.0: USB HC takeover failed!  (BIOS/SMM bug)
[   14.619415] ohci_hcd 0000:00:12.0: can't setup
[   14.624264] ohci_hcd 0000:00:12.0: USB bus 1 deregistered
[   14.630262] ohci_hcd 0000:00:12.0: PCI INT A disabled
[   14.635877] ohci_hcd 0000:00:12.0: init 0000:00:12.0 fail, -16
[   14.642263] ohci_hcd: probe of 0000:00:12.0 failed with error -16
[   14.649008] ohci_hcd 0000:00:12.1: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[   14.656848] ohci_hcd 0000:00:12.1: OHCI Host Controller
[   14.662579] ohci_hcd 0000:00:12.1: new USB bus registered, assigned bus number 1
[   22.668004] ohci_hcd 0000:00:12.1: USB HC takeover failed!  (BIOS/SMM bug)
[   22.675470] ohci_hcd 0000:00:12.1: can't setup
[   22.680290] ohci_hcd 0000:00:12.1: USB bus 1 deregistered
[   22.686118] ohci_hcd 0000:00:12.1: PCI INT A disabled
[   22.691742] ohci_hcd 0000:00:12.1: init 0000:00:12.1 fail, -16
[   22.698163] ohci_hcd: probe of 0000:00:12.1 failed with error -16
[   22.704836] ohci_hcd 0000:00:13.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
[   22.712793] ohci_hcd 0000:00:13.0: OHCI Host Controller
[   22.718541] ohci_hcd 0000:00:13.0: new USB bus registered, assigned bus number 1
[   30.724004] ohci_hcd 0000:00:13.0: USB HC takeover failed!  (BIOS/SMM bug)
[   30.731397] ohci_hcd 0000:00:13.0: can't setup
[   30.736232] ohci_hcd 0000:00:13.0: USB bus 1 deregistered
[   30.742097] ohci_hcd 0000:00:13.0: PCI INT A disabled
[   30.747628] ohci_hcd 0000:00:13.0: init 0000:00:13.0 fail, -16
[   30.754124] ohci_hcd: probe of 0000:00:13.0 failed with error -16
[   30.760783] ohci_hcd 0000:00:13.1: PCI INT A -> GSI 18 (level, low) -> IRQ 18
[   30.768663] ohci_hcd 0000:00:13.1: OHCI Host Controller
[   30.774442] ohci_hcd 0000:00:13.1: new USB bus registered, assigned bus number 1
[   38.796004] ohci_hcd 0000:00:13.1: USB HC takeover failed!  (BIOS/SMM bug)
[   38.803405] ohci_hcd 0000:00:13.1: can't setup
[   38.808328] ohci_hcd 0000:00:13.1: USB bus 1 deregistered
[   38.814324] ohci_hcd 0000:00:13.1: PCI INT A disabled
[   38.819841] ohci_hcd 0000:00:13.1: init 0000:00:13.1 fail, -16
[   38.826275] ohci_hcd: probe of 0000:00:13.1 failed with error -16
[   38.833071] ohci_hcd 0000:00:14.5: PCI INT C -> GSI 18 (level, low) -> IRQ 18
[   38.840934] ohci_hcd 0000:00:14.5: OHCI Host Controller
[   38.846780] ohci_hcd 0000:00:14.5: new USB bus registered, assigned bus number 1
[   46.852004] ohci_hcd 0000:00:14.5: USB HC takeover failed!  (BIOS/SMM bug)
[   46.859434] ohci_hcd 0000:00:14.5: can't setup
[   46.864302] ohci_hcd 0000:00:14.5: USB bus 1 deregistered
[   46.870312] ohci_hcd 0000:00:14.5: PCI INT C disabled
[   46.875922] ohci_hcd 0000:00:14.5: init 0000:00:14.5 fail, -16
[   46.882333] ohci_hcd: probe of 0000:00:14.5 failed with error -16
Begin: Loading essential drivers ... done.
Begin: Running /scripts/init-premount ... done.


It seems that also the USB controller initialization fails, although I did not test if it worked.

Aside from the AHCI/OHCI/EHCI -drivers failing, the boot logs seem to be the same as before.

I tried to look at the patch code, but could not figure out why this is happening.

Best regards,
Juhana Helovuo

Patch

Index: svn/src/arch/i386/boot/multiboot.c
===================================================================
--- svn.orig/src/arch/i386/boot/multiboot.c
+++ svn/src/arch/i386/boot/multiboot.c
@@ -22,62 +22,16 @@ 
 #include <string.h>
 #include <device/resource.h>
 #include <console/console.h>
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
 
-static struct multiboot_mmap_entry *mb_mem;
 struct multiboot_info *mbi = NULL;
 
-static struct {
-	u64 addr;
-	u64 len;
-} reserved_mem[2];
-
-static void build_mb_mem_range_nooverlap(u64 addr, u64 len)
-{
-	int i;
-	for (i = 0; i < sizeof(reserved_mem) / sizeof(reserved_mem[0]); i++) {
-		/* free region fully contained in reserved region, abort */
-		if (addr >= reserved_mem[i].addr && addr + len <= reserved_mem[i].addr + reserved_mem[i].len)
-			return;
-		/* reserved region splits free region */
-		if (addr < reserved_mem[i].addr && addr + len > reserved_mem[i].addr + reserved_mem[i].len) {
-			build_mb_mem_range_nooverlap(addr, reserved_mem[i].addr - addr);
-			build_mb_mem_range_nooverlap(reserved_mem[i].addr + reserved_mem[i].len, (addr + len) - (reserved_mem[i].addr + reserved_mem[i].len));
-			return;
-		}
-		/* left overlap */
-		if (addr < reserved_mem[i].addr + reserved_mem[i].len && addr + len > reserved_mem[i].addr + reserved_mem[i].len) {
-			len += addr;
-			addr = reserved_mem[i].addr + reserved_mem[i].len;
-			len -= addr;
-			/* len += addr - old_addr */
-			continue;
-		}
-		/* right overlap */
-		if (addr < reserved_mem[i].addr && addr + len > reserved_mem[i].addr) {
-			len = reserved_mem[i].addr - addr;
-			continue;
-		}
-		/* none of the above, just add it */
-	}
-
-	mb_mem->addr = addr;
-	mb_mem->len = len;
-	mb_mem->type = 1;
-	mb_mem->size = sizeof(*mb_mem) - sizeof(mb_mem->size);
-	mb_mem++;
-}
-
-static void build_mb_mem_range(void *gp, struct device *dev, struct resource *res)
-{
-	build_mb_mem_range_nooverlap(res->base, res->size);
-}
-
-#define ROUND(_r,_a) (((_r) + (((_a) - 1))) & ~((_a) - 1))
-
-unsigned long write_multiboot_info(
-	unsigned long low_table_start, unsigned long low_table_end,
-	unsigned long rom_table_start, unsigned long rom_table_end)
+unsigned long write_multiboot_info(unsigned long rom_table_end)
 {
+	static struct multiboot_mmap_entry *mb_mem;
+	struct lb_memory* coreboot_table;
+	int entries;
 	int i;
 
 	mbi = (struct multiboot_info *)rom_table_end;
@@ -88,26 +42,31 @@  unsigned long write_multiboot_info(
 	mbi->mmap_addr = (u32) rom_table_end;
 	mb_mem = (struct multiboot_mmap_entry *)rom_table_end;
 
-	/* FIXME This code is broken, it does not know about high memory
-	 * tables, nor does it reserve the coreboot table area.
-	 */
-	/* reserved regions */
-	reserved_mem[0].addr = low_table_start;
-	reserved_mem[0].len = ROUND(low_table_end - low_table_start, 4096);
-	reserved_mem[1].addr = rom_table_start;
-	reserved_mem[1].len = ROUND(rom_table_end - rom_table_start, 4096);
-
-	for (i = 0; i < sizeof(reserved_mem) / sizeof(reserved_mem[0]); i++) {
-		mb_mem->addr = reserved_mem[i].addr;
-		mb_mem->len = reserved_mem[i].len;
-		mb_mem->type = 2;
-		mb_mem->size = sizeof(*mb_mem) - sizeof(mb_mem->size);
-		mb_mem++;
+	/* copy regions from coreboot tables */
+	coreboot_table = get_lb_mem();
+	entries = (coreboot_table->size - sizeof(*coreboot_table))/sizeof(coreboot_table->map[0]);
+
+	if (coreboot_table == NULL || entries < 1) {
+	    printk(BIOS_INFO, "%s: Cannot find coreboot table.\n", __func__);
+	    return (unsigned long) mb_mem;
 	}
 
-	/* free regions */
-	search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE,
-		IORESOURCE_MEM | IORESOURCE_CACHEABLE, build_mb_mem_range, NULL);
+	for (i = 0; i < entries; i++) {
+	  uint64_t entry_start = unpack_lb64(coreboot_table->map[i].start);
+	  uint64_t entry_size = unpack_lb64(coreboot_table->map[i].size);
+	  mb_mem->addr = entry_start;
+	  mb_mem->len = entry_size;
+	  switch (coreboot_table->map[i].type) {
+	    case LB_MEM_RAM:
+	      mb_mem->type = MULTIBOOT_MEMORY_AVAILABLE;
+	      break;
+	    default: // anything other than usable RAM
+	      mb_mem->type = MULTIBOOT_MEMORY_RESERVED;
+	      break;
+	  }
+	  mb_mem->size = sizeof(*mb_mem) - sizeof(mb_mem->size);
+	  mb_mem++;
+	}
 
 	mbi->mmap_length = ((u32) mb_mem) - mbi->mmap_addr;
 	mbi->flags |= MB_INFO_MEM_MAP;
Index: svn/src/arch/i386/boot/tables.c
===================================================================
--- svn.orig/src/arch/i386/boot/tables.c
+++ svn/src/arch/i386/boot/tables.c
@@ -179,14 +179,6 @@  struct lb_memory *write_tables(void)
 
 #endif
 
-#if CONFIG_MULTIBOOT
-	post_code(0x9d);
-
-	/* The Multiboot information structure */
-	rom_table_end = write_multiboot_info(
-				low_table_start, low_table_end,
-				rom_table_start, rom_table_end);
-#endif
 
 #define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
 	post_code(0x9d);
@@ -210,8 +202,9 @@  struct lb_memory *write_tables(void)
 				new_high_table_pointer - high_table_pointer);
 	} else {
 		/* The coreboot table must be in 0-4K or 960K-1M */
-		write_coreboot_table(low_table_start, low_table_end,
-			      rom_table_start, rom_table_end);
+		rom_table_end = write_coreboot_table(
+				     low_table_start, low_table_end,
+				     rom_table_start, rom_table_end);
 	}
 
 	post_code(0x9e);
@@ -224,6 +217,13 @@  struct lb_memory *write_tables(void)
 	cbmem_add(CBMEM_ID_RESUME, 1024 * (1024-64));
 #endif
 
+#if CONFIG_MULTIBOOT
+	post_code(0x9d);
+
+	/* The Multiboot information structure */
+	write_multiboot_info(rom_table_end);
+#endif
+
 	// Remove before sending upstream
 	cbmem_list();
 
Index: svn/src/include/cpu/x86/multiboot.h
===================================================================
--- svn.orig/src/include/cpu/x86/multiboot.h
+++ svn/src/include/cpu/x86/multiboot.h
@@ -167,6 +167,9 @@  struct multiboot_info {
 	uint16_t vbe_interface_len;
 };
 
+#define MULTIBOOT_MEMORY_AVAILABLE              1
+#define MULTIBOOT_MEMORY_RESERVED               2
+
 struct multiboot_mmap_entry {
 	uint32_t size;
 	uint64_t addr;
@@ -176,6 +179,6 @@  struct multiboot_mmap_entry {
 
 extern struct multiboot_info *mbi;
 
-unsigned long  write_multiboot_info(unsigned long, unsigned long, unsigned long, unsigned long);
+unsigned long  write_multiboot_info(unsigned long rom_table_end);
 
 #endif