Patchwork Add a board-enable for the ASRock K7S41, chipset-enable for SiS 741

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Submitter Uwe Hermann
Date 2010-09-11 16:09:27
Message ID <20100911160927.GH19625@greenwood>
Download mbox | patch
Permalink /patch/1918/
State Accepted
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Comments

Uwe Hermann - 2010-09-11 16:09:27
See patch.

I literally guessed this board-enable and was lucky at the very first try :)

Not sure if DMI matching is required (I guess it is), please let me know
if I should change that.

lspci/superiotool/flashrom -w are attached.


Uwe.
Joshua Roys - 2010-09-14 14:55:32
On 09/11/2010 12:09 PM, Uwe Hermann wrote:
> See patch.
> 
> I literally guessed this board-enable and was lucky at the very first try :)
> 
> Not sure if DMI matching is required (I guess it is), please let me know
> if I should change that.
> 
> lspci/superiotool/flashrom -w are attached.
> 
> 
> Uwe.
> 

Two things,

This one will conflict with:
http://patchwork.coreboot.org/patch/1927/

Other than that, if you're going to do DMI (which isn't strictly needed
right now- I don't see anything in board_enable.c we could conflict
with, but who knows in the future) I would just match on the SMBus even
though it doesn't have subsystem IDs.  That may be a personal preference
though, so feel free to disagree.

Josh
Carl-Daniel Hailfinger - 2010-10-05 21:35:02
On 11.09.2010 18:09, Uwe Hermann wrote:
> I literally guessed this board-enable and was lucky at the very first try :)
>
> Not sure if DMI matching is required (I guess it is), please let me know
> if I should change that.
>
> lspci/superiotool/flashrom -w are attached.
>   

Could you add a link to the mail at flashrom.org with the logs? That
would be nice for people who go through the changelog and not the
mailing list.

> Add a board-enable for the ASRock K7S41, chipset-enable for SiS 741.
>
> This also adds (and marks as tested) a chipset-enable for the SiS 741.
>
> All operations successfully tested on hardware.
>
> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>

I agree with David Borg that we want the real fix (Super I/O
autodetection and auto-setup), but given that the Super I/O probing
needs to be revamped, I think this is a lower risk patch.

I want to merge David's patches directly after 0.9.3 is out, though:
[flashrom] [PATCH] W83697 superio safety checks
[flashrom] [PATCH] W83697xx superio flash enable
[flashrom] [Patch] Reduce usage of w836xx_memw

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Regards,
Carl-Daniel
Uwe Hermann - 2010-10-05 21:50:01
On Tue, Oct 05, 2010 at 11:35:02PM +0200, Carl-Daniel Hailfinger wrote:
> On 11.09.2010 18:09, Uwe Hermann wrote:
> > I literally guessed this board-enable and was lucky at the very first try :)
> >
> > Not sure if DMI matching is required (I guess it is), please let me know
> > if I should change that.
> >
> > lspci/superiotool/flashrom -w are attached.
> >   
> 
> Could you add a link to the mail at flashrom.org with the logs? That
> would be nice for people who go through the changelog and not the
> mailing list.

Done.

 
> I agree with David Borg that we want the real fix (Super I/O
> autodetection and auto-setup), but given that the Super I/O probing
> needs to be revamped, I think this is a lower risk patch.
> 
> I want to merge David's patches directly after 0.9.3 is out, though:
> [flashrom] [PATCH] W83697 superio safety checks
> [flashrom] [PATCH] W83697xx superio flash enable
> [flashrom] [Patch] Reduce usage of w836xx_memw

Yep, agreed.

 
> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Thanks, r1192.


Uwe.

Patch

Add a board-enable for the ASRock K7S41, chipset-enable for SiS 741.

This also adds (and marks as tested) a chipset-enable for the SiS 741.

All operations successfully tested on hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>

Index: chipset_enable.c
===================================================================
--- chipset_enable.c	(Revision 1158)
+++ chipset_enable.c	(Arbeitskopie)
@@ -1135,6 +1135,7 @@ 
 	{0x1039, 0x0733, NT, "SiS", "733",		enable_flash_sis540},
 	{0x1039, 0x0735, OK, "SiS", "735",		enable_flash_sis540},
 	{0x1039, 0x0740, NT, "SiS", "740",		enable_flash_sis540},
+	{0x1039, 0x0741, OK, "SiS", "741",		enable_flash_sis540},
 	{0x1039, 0x0745, OK, "SiS", "745",		enable_flash_sis540},
 	{0x1039, 0x0746, NT, "SiS", "746",		enable_flash_sis540},
 	{0x1039, 0x0748, NT, "SiS", "748",		enable_flash_sis540},
Index: print.c
===================================================================
--- print.c	(Revision 1158)
+++ print.c	(Arbeitskopie)
@@ -306,6 +306,7 @@ 
 	B("ASRock",	"A330GC",		1, "http://www.asrock.com/mb/overview.asp?Model=A330GC", NULL),
 	B("ASRock",	"A770CrossFire",	1, "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b", NULL),
 	B("ASRock",	"ALiveNF6G-DVI",	1, "http://www.asrock.com/mb/overview.asp?Model=ALiveNF6G-DVI", NULL),
+	B("ASRock",	"K7S41",		1, "http://www.asrock.com/mb/overview.asp?Model=K7S41", NULL),
 	B("ASRock",	"K7VT4A+",		0, "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=", "No chip found, probably due to flash translation. http://www.flashrom.org/pipermail/flashrom/2009-August/000393.html"),
 	B("ASRock",	"K8S8X",		1, "http://www.asrock.com/mb/overview.asp?Model=K8S8X", NULL),
 	B("ASRock",	"M3A790GXH/128M",	1, "http://www.asrock.com/MB/overview.asp?Model=M3A790GXH/128M", NULL),
Index: board_enable.c
===================================================================
--- board_enable.c	(Revision 1158)
+++ board_enable.c	(Arbeitskopie)
@@ -390,6 +390,7 @@ 
  *  - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
  *  - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
  *  - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
+ *  - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
  */
 static int w836xx_memw_enable_2e(void)
 {
@@ -1789,6 +1790,7 @@ 
 	{0x1106, 0x3177, 0x17F2, 0x3177,  0x1106, 0x3148, 0x17F2, 0x3148, NULL,          NULL,         NULL,          "Albatron",    "PM266A Pro",            0,   OK, w836xx_memw_enable_2e},
 	{0x1022, 0x2090,      0,      0,  0x1022, 0x2080,      0,      0, NULL,          "artecgroup", "dbe61",       "Artec Group", "DBE61",                 0,   OK, board_artecgroup_dbe6x},
 	{0x1022, 0x2090,      0,      0,  0x1022, 0x2080,      0,      0, NULL,          "artecgroup", "dbe62",       "Artec Group", "DBE62",                 0,   OK, board_artecgroup_dbe6x},
+	{0x1039, 0x0741, 0x1849, 0x0741,  0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $",    NULL,         NULL,          "ASRock",      "K7S41",                 0,   OK, w836xx_memw_enable_2e},
 	{0x8086, 0x24D4, 0x1849, 0x24D0,  0x8086, 0x24D5, 0x1849, 0x9739, NULL,          NULL,         NULL,          "ASRock",      "P4i65GV",               0,   OK, intel_ich_gpio23_raise},
 	{0x8086, 0x2570, 0x1849, 0x2570,  0x8086, 0x24d3, 0x1849, 0x24d0, NULL,          NULL,         NULL,          "ASRock",      "775i65G",               0,   OK, intel_ich_gpio23_raise},
 	{0x1106, 0x3189, 0x1043, 0x807F,  0x1106, 0x3065, 0x1043, 0x80ED, NULL,          NULL,         NULL,          "ASUS",        "A7V600-X",              0,   OK, it8712f_gpio3_1_raise},