| Submitter | Scott |
|---|---|
| Date | 2010-09-14 03:07:50 |
| Message ID | <2EB0521595C845F79F340D266EE6D5B8@m3a78> |
| Download | mbox | patch |
| Permalink | /patch/1932/ |
| State | Accepted |
| Headers | show |
Comments
On Mon, Sep 13, 2010 at 9:07 PM, Scott Duplichan <scott@notabs.org> wrote: > This patch corrects a coding error in the original implementation > of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code > sets msr c001_102a bit 3 when bit 35 was intended. > > > Signed-off-by: Scott Duplichan <scott@notabs.org> > > Index: src/cpu/amd/car/cache_as_ram.inc > =================================================================== > --- src/cpu/amd/car/cache_as_ram.inc (revision 5813) > +++ src/cpu/amd/car/cache_as_ram.inc (working copy) > @@ -129,8 +129,8 @@ > /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */ > rdmsr > > - /* Set bit 35 to 1 in EAX */ > - bts $35, %eax > + /* Set bit 35 to 1 in EDX:EAX */ > + bts $35-32, %edx > > /* write back the modified register EDX:EAX to the MSR specified in ECX */ > wrmsr > Nice catch Scott. That for all the help recently. Acked-by: Marc Jones <marcj303@gmail.com> r5814 Marc
Patch
Index: src/cpu/amd/car/cache_as_ram.inc =================================================================== --- src/cpu/amd/car/cache_as_ram.inc (revision 5813) +++ src/cpu/amd/car/cache_as_ram.inc (working copy) @@ -129,8 +129,8 @@ /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */ rdmsr - /* Set bit 35 to 1 in EAX */ - bts $35, %eax + /* Set bit 35 to 1 in EDX:EAX */ + bts $35-32, %edx /* write back the modified register EDX:EAX to the MSR specified in ECX */ wrmsr
This patch corrects a coding error in the original implementation of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code sets msr c001_102a bit 3 when bit 35 was intended. Signed-off-by: Scott Duplichan <scott@notabs.org>