Patchwork Add Broadcom OSB4 chipset enable / parallel flash chips

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Submitter Joshua Roys
Date 2010-09-15 14:34:26
Message ID <4C90D972.3010408@gmail.com>
Download mbox | patch
Permalink /patch/1949/
State Accepted
Commit 1176
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Comments

Joshua Roys - 2010-09-15 14:34:26
Hello,

Awesome!  I'm glad you got it working.

On 09/15/2010 06:19 AM, Carl-Daniel Hailfinger wrote:
> Funny. The 0xc6f access looks very similar to parts of the SB400 chipset
> enable. (Side note: we should ask AMD if the SB400 chipset enable is
> correct.)
> 

Yes, I noticed the same thing- hence the placement in chipset_enable.c.

> Joshua, I would like this in 0.9.3. Would it be OK for you to split the
> patch in a chipset enable and a flash chip addition? If possible,
> coordinate with Mattias to avoid conflicts in flashchips.[ch]
> 

OK, attached are two separate patches and a diff...  if the chip #define
fixup gets applied first, then use the post-prefix-change.diff.txt and
squash it in with the flash chip patch.  Otherwise that patch will have
to be updated in order to account for these chips.  (I'll try to figure
out on IRC what order these will be in, and if needs be I can spin
another patch set.)

Thanks!

Signed-off-by: Joshua Roys <roysjosh@gmail.com>

Josh
From dde743cbcbbefadbecbbfc22e8d040ae2a7c3e87 Mon Sep 17 00:00:00 2001
From: Joshua Roys <roysjosh@gmail.com>
Date: Wed, 15 Sep 2010 09:23:53 -0400
Subject: [PATCH] Add some parallel flash chips

Bright BM29F040:
http://www.datasheetcatalog.org/datasheet/WinbondElectronics/mXxvzzr.pdf
Hyundai HY29F040A:
http://www.datasheetarchive.com/pdf/getfile.php?dir=Datasheets-30&file=DSA-594844.pdf
Macronix MX29F040:
http://pdf1.alldatasheet.com/datasheet-pdf/view/74482/MCNIX/MX29F040.html

Signed-off-by: Joshua Roys <roysjosh@gmail.com>
---
 flashchips.c |   78 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 flashchips.h |    4 +++
 2 files changed, 82 insertions(+), 0 deletions(-)
Mattias Mattsson - 2010-09-16 00:53:20
On Wed, Sep 15, 2010 at 16:34, Joshua Roys <roysjosh@gmail.com> wrote:
> Hello,
>
> Awesome!  I'm glad you got it working.
>
> On 09/15/2010 06:19 AM, Carl-Daniel Hailfinger wrote:
>> Funny. The 0xc6f access looks very similar to parts of the SB400 chipset
>> enable. (Side note: we should ask AMD if the SB400 chipset enable is
>> correct.)
>>
>
> Yes, I noticed the same thing- hence the placement in chipset_enable.c.
>
>> Joshua, I would like this in 0.9.3. Would it be OK for you to split the
>> patch in a chipset enable and a flash chip addition? If possible,
>> coordinate with Mattias to avoid conflicts in flashchips.[ch]
>>
>
> OK, attached are two separate patches and a diff...  if the chip #define
> fixup gets applied first, then use the post-prefix-change.diff.txt and
> squash it in with the flash chip patch.  Otherwise that patch will have
> to be updated in order to account for these chips.  (I'll try to figure
> out on IRC what order these will be in, and if needs be I can spin
> another patch set.)
>
> Thanks!
>
> Signed-off-by: Joshua Roys <roysjosh@gmail.com>

Thanks!

Flash chip part
Acked-by: Mattias Mattsson <vitplister@gmail.com>

Fixed a small typo (TEST_PR -> TEST_OK_PR), added two more Bright chip
IDs and committed as r1176.


-mattias

Patch

diff --git a/flashchips.c b/flashchips.c
index 3ab19bb..5e881da 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -1962,6 +1962,32 @@  struct flashchip flashchips[] = {
 	},
 
 	{
+		.vendor		= "Bright",
+		.name		= "BM29F040",
+		.bustype	= CHIP_BUSTYPE_PARALLEL,
+		.manufacture_id	= BRIGHT_ID,
+		.model_id	= BRIGHT_BM29F040,
+		.total_size	= 512,
+		.page_size	= 64 * 1024,
+		.feature_bits	= FEATURE_EITHER_RESET,
+		.tested		= TEST_PR,
+		.probe		= probe_jedec,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {64 * 1024, 8} },
+				.block_erase = erase_sector_jedec,
+			}, {
+				.eraseblocks = { {512 * 1024, 1} },
+				.block_erase = erase_chip_block_jedec,
+			},
+		},
+		.write		= write_jedec_1,
+		.read		= read_memmapped,
+	},
+
+	{
 		.vendor		= "EMST",
 		.name		= "F49B002UA",
 		.bustype	= CHIP_BUSTYPE_PARALLEL,
@@ -3085,6 +3111,32 @@  struct flashchip flashchips[] = {
 	},
 
 	{
+		.vendor		= "Hyundai",
+		.name		= "HY29F040A",
+		.bustype	= CHIP_BUSTYPE_PARALLEL,
+		.manufacture_id	= HYUNDAI_ID,
+		.model_id	= HY_29F040A,
+		.total_size	= 512,
+		.page_size	= 64 * 1024,
+		.feature_bits	= FEATURE_ADDR_2AA | FEATURE_EITHER_RESET,
+		.tested		= TEST_UNTESTED,
+		.probe		= probe_jedec,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {64 * 1024, 8} },
+				.block_erase = erase_sector_jedec,
+			}, {
+				.eraseblocks = { {512 * 1024, 1} },
+				.block_erase = erase_chip_block_jedec,
+			},
+		},
+		.write		= write_jedec_1,
+		.read		= read_memmapped,
+	},
+
+	{
 		.vendor		= "Intel",
 		.name		= "28F001BX-B",
 		.bustype	= CHIP_BUSTYPE_PARALLEL,
@@ -3883,6 +3935,32 @@  struct flashchip flashchips[] = {
 
 	{
 		.vendor		= "Macronix",
+		.name		= "MX29F040",
+		.bustype	= CHIP_BUSTYPE_PARALLEL,
+		.manufacture_id	= MX_ID,
+		.model_id	= MX_29F040,
+		.total_size	= 512,
+		.page_size	= 64 * 1024,
+		.feature_bits	= FEATURE_ADDR_2AA | FEATURE_SHORT_RESET,
+		.tested		= TEST_UNTESTED,
+		.probe		= probe_jedec,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {64 * 1024, 8} },
+				.block_erase = erase_sector_jedec,
+			}, {
+				.eraseblocks = { {512 * 1024, 1} },
+				.block_erase = erase_chip_block_jedec,
+			},
+		},
+		.write		= write_jedec_1,
+		.read		= read_memmapped,
+	},
+
+	{
+		.vendor		= "Macronix",
 		.name		= "MX29LV040",
 		.bustype	= CHIP_BUSTYPE_PARALLEL,
 		.manufacture_id	= MX_ID,
diff --git a/flashchips.h b/flashchips.h
index 2ca1163..f841aaa 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -171,6 +171,10 @@ 
 #define AT_49F002N		0x07	/* for AT49F002(N)  */
 #define AT_49F002NT		0x08	/* for AT49F002(N)T */
 
+/* Bright Microelectronics has the same manufacturer ID as Hyundai... */
+#define BRIGHT_ID		0xAD	/* Bright Microelectronics */
+#define BRIGHT_BM29F040		0x40
+
 #define CATALYST_ID		0x31	/* Catalyst */
 
 #define EMST_ID			0x8C	/* EMST / EFST Elite Flash Storage */