From patchwork Fri Sep 17 14:48:38 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [RFC] sata PHY settings callback on SB700 Date: Fri, 17 Sep 2010 14:48:38 -0000 From: Rudolf Marek X-Patchwork-Id: 1956 Message-Id: <4C937FC6.6060003@assembler.cz> To: Coreboot Hi from Fort Worth, Here is a proposed way how to handle the SATA PHY settings on SB700. It consists of weak function which always exists (with defaults) and a possibility to override this with normal function in main.c. This is the other way of doing that and not using the devictree.cb. Please tell if it is ok this way. I suggest all people who ported SB700 should have a look on their SATA PHY settings too because it is most likely PCB/MB dependent. This patch is not tested but it could work. Signed-off-by: Rudolf Marek My holiday ends soonish but I temped to do bit of stuff during El Paso - Forth Worth ride ;) Thanks, Rudolf Acked-by: Peter Stuge Index: src/southbridge/amd/sb700/sb700.h =================================================================== --- src/southbridge/amd/sb700/sb700.h (revision 5814) +++ src/southbridge/amd/sb700/sb700.h (working copy) @@ -52,6 +52,11 @@ #ifdef __PRE_RAM__ void sb700_lpc_port80(void); void sb700_pci_port80(void); +#else +#include +/* allow override in mainboard.c */ +void sb700_setup_sata_phys(struct device *dev); + #endif #endif /* SB700_H */ Index: src/southbridge/amd/sb700/sb700_sata.c =================================================================== --- src/southbridge/amd/sb700/sb700_sata.c (revision 5814) +++ src/southbridge/amd/sb700/sb700_sata.c (working copy) @@ -53,6 +53,29 @@ return 0; } + /* This function can be overloaded in mainboard.c */ + +void __attribute__((weak)) sb700_setup_sata_phys(struct device *dev) { + /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ + pci_write_config16(dev, 0x86, 0x2c00); + + /* RPR7.6.2 SATA GENI PHY ports setting */ + pci_write_config32(dev, 0x88, 0x01B48017); + pci_write_config32(dev, 0x8c, 0x01B48019); + pci_write_config32(dev, 0x90, 0x01B48016); + pci_write_config32(dev, 0x94, 0x01B48016); + pci_write_config32(dev, 0x98, 0x01B48016); + pci_write_config32(dev, 0x9C, 0x01B48016); + + /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ + pci_write_config16(dev, 0xA0, 0xA09A); + pci_write_config16(dev, 0xA2, 0xA09F); + pci_write_config16(dev, 0xA4, 0xA07A); + pci_write_config16(dev, 0xA6, 0xA07A); + pci_write_config16(dev, 0xA8, 0xA07A); + pci_write_config16(dev, 0xAA, 0xA07A); +} + static void sata_init(struct device *dev) { u8 byte; @@ -161,27 +184,7 @@ /* Program the watchdog counter to 0x10 */ byte = 0x10; pci_write_config8(dev, 0x46, byte); - - /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ - word = 0x2c00; - pci_write_config16(dev, 0x86, word); - - /* RPR7.6.2 SATA GENI PHY ports setting */ - pci_write_config32(dev, 0x88, 0x01B48017); - pci_write_config32(dev, 0x8c, 0x01B48019); - pci_write_config32(dev, 0x90, 0x01B48016); - pci_write_config32(dev, 0x94, 0x01B48016); - pci_write_config32(dev, 0x98, 0x01B48016); - pci_write_config32(dev, 0x9C, 0x01B48016); - - /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ - pci_write_config16(dev, 0xA0, 0xA09A); - pci_write_config16(dev, 0xA2, 0xA09F); - pci_write_config16(dev, 0xA4, 0xA07A); - pci_write_config16(dev, 0xA6, 0xA07A); - pci_write_config16(dev, 0xA8, 0xA07A); - pci_write_config16(dev, 0xAA, 0xA07A); - + sb700_setup_sata_phys(dev); /* Enable the I/O, MM, BusMaster access for SATA */ byte = pci_read_config8(dev, 0x4); byte |= 7 << 0; Index: src/mainboard/asrock/939a785gmh/mainboard.c =================================================================== --- src/mainboard/asrock/939a785gmh/mainboard.c (revision 5814) +++ src/mainboard/asrock/939a785gmh/mainboard.c (working copy) @@ -147,3 +147,25 @@ CHIP_NAME("Asrock 939A785GMH/128M Mainboard") .enable_dev = mb_enable, }; + +/* override the default SATA PHY setup */ +void sb700_setup_sata_phys(struct device *dev) { + /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ + pci_write_config16(dev, 0x86, 0x2c00); + + /* RPR7.6.2 SATA GENI PHY ports setting */ + pci_write_config32(dev, 0x88, 0x01B48016); + pci_write_config32(dev, 0x8c, 0x01B48016); + pci_write_config32(dev, 0x90, 0x01B48016); + pci_write_config32(dev, 0x94, 0x01B48016); + pci_write_config32(dev, 0x98, 0x01B48016); + pci_write_config32(dev, 0x9C, 0x01B48016); + + /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ + pci_write_config16(dev, 0xA0, 0xA07A); + pci_write_config16(dev, 0xA2, 0xA07A); + pci_write_config16(dev, 0xA4, 0xA07A); + pci_write_config16(dev, 0xA6, 0xA07A); + pci_write_config16(dev, 0xA8, 0xA07A); + pci_write_config16(dev, 0xAA, 0xA0FF); +} Index: src/mainboard/asus/p2b/romstage.c.orig =================================================================== Index: src/mainboard/asus/p2b/acpi_tables.c =================================================================== Index: src/mainboard/asus/p2b/dsdt.asl ===================================================================