Patchwork : AMD DDR3 fix the register name

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Submitter Bao, Zheng
Date 2010-09-19 07:05:19
Message ID <DD1CC71B621B004FA76856E5129D6B170424D11A@sbjgexmb1.amd.com>
Download mbox | patch
Permalink /patch/1961/
State Accepted
Commit r5821
Headers show

Comments

Bao, Zheng - 2010-09-19 07:05:19
Fix the typo. Field DisAutoRefresh is in DramTimngHi.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>

 	Set_NB32(dev, 0x8c + reg_off, DramTimingHi);	/*DCT Timing
Hi*/
Fix the typo. Field DisAutoRefresh is in DramTimngHi.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Marc Jones - 2010-09-20 20:10:15
On Sun, Sep 19, 2010 at 1:05 AM, Bao, Zheng <Zheng.Bao@amd.com> wrote:
> Fix the typo. Field DisAutoRefresh is in DramTimngHi.
>
> Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>

Patch

Index: src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
===================================================================
--- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c	(revision 5818)
+++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c	(working copy)
@@ -1220,7 +1220,7 @@ 
 	Set_NB32(dev, 0x88 + reg_off, DramTimingLo);	/*DCT Timing Low*/
 
 	if (pDCTstat->Speed > 4) {
-		DramTimingLo |= 1 << DisAutoRefresh;
+		DramTimingHi |= 1 << DisAutoRefresh;
 	}
 	DramTimingHi |= 0x000018FF;
 	Set_NB32(dev, 0x8c + reg_off, DramTimingHi);	/*DCT Timing Hi*/