Patchwork Kconfig support for M57SLI

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Submitter Harald Gutmann
Date 2009-08-26 18:14:39
Message ID <200908262014.39385.harald.gutmann@gmx.net>
Download mbox | patch
Permalink /patch/200/
State Accepted
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Comments

Harald Gutmann - 2009-08-26 18:14:39
Hmm... Why do I so often forget that I should/want to attach something?

Here it is.

Note: The devicetree.cb just contains some cleanup and whitespace fixes. There 
have no "changes" been done on that file.

On Wednesday 26 August 2009 20:09:32 Harald Gutmann wrote:
> Here is my new version of the Kconfig patch for M57SLI.
>
> It does build, but there are some warnings about CONFIG_* values not
> defined.
>
> Right now I have not tested the generated images, but I think I can do that
> tomorrow.
> When the images work, it will get the "Signed-off" tag.
>
> Thanks to Myles Watson and Christi Magherusan for helping out in various
> themes according this patch and the understanding of Kconfig.
>
>
> Kind regards,
> Harald
Uwe Hermann - 2009-08-28 17:44:39
On Wed, Aug 26, 2009 at 08:14:39PM +0200, Harald Gutmann wrote:
> Index: src/mainboard/gigabyte/m57sli/Kconfig
> ===================================================================
> --- src/mainboard/gigabyte/m57sli/Kconfig	(revision 0)
> +++ src/mainboard/gigabyte/m57sli/Kconfig	(revision 0)
> @@ -0,0 +1,197 @@
> +choice
> +	prompt "Mainboard model"
> +	depends on VENDOR_GIGABYTE

Please check current svn, we use a different method for this now.
src/mainboard/gigabyte/Kconfig includes all board files.

Example: src/mainboard/asus/Kconfig and src/mainboard/asus/p2b-f/Kconfig


> +config BOARD_GIGABYTE_M57SLI
> +	bool "M57SLI"

Full names as per vendor website please, in this case:

config BOARD_GIGABYTE_GA_M57SLI_S4
	bool "GA-M57SLI-S4"

There are multiple occurences below, please fix them all.


> +	select ARCH_X86
> +	select CPU_AMD_K8
> +	select CPU_AMD_SOCKET_AM2
> +	select NORTHBRIDGE_AMD_AMDK8
> +	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
> +	select SOUTHBRIDGE_NVIDIA_MCP55
> +	select SUPERIO_ITE_IT8716F
> +	select PIRQ_TABLE

HAVE_PIRQ_TABLE


> +	select USE_PRINTK_IN_CAR
> +	help
> +	Gigabyte M57SLI mainboard	
> +endchoice
> +
> +config MAINBOARD_DIR
> +	string
> +	default gigabyte/m57sli 
                         ^^^^^^^
  This is the only exception, should stay "m57sli" as it's a dirname.


> +	depends on BOARD_GIGABYTE_M57SLI
> +
> +config USE_DCACHE_RAM
> +	int

Should be bool, but this is no longer needed as of recent svn,
you can use "select USE_DCACHE_RAM" above.
Or just drop it, the default is y anyway in src/cpu/amd/model_fxx/Kconfig.


> +	default 1
> +	depends on BOARD_GIGABYTE_M57SLI
> +	
> +config DCACHE_RAM_BASE
> +	hex
> +	default 0xc8000
> +	depends on BOARD_GIGABYTE_M57SLI
> +	
> +config DCACHE_RAM_SIZE
> +	hex
> +	default 0x08000
> +	depends on BOARD_GIGABYTE_M57SLI
> +
> +config DCACHE_RAM_GLOBAL_VAR_SIZE
> +	hex
> +	default 0x01000
> +	depends on BOARD_GIGABYTE_M57SLI

These three also also no longer needed, pre-defined in
src/cpu/amd/model_fxx/Kconfig.


> +config APIC_ID_OFFSET
> +	int
> +	default 16
> +	depends on BOARD_GIGABYTE_M57SLI
> +
> +config HAVE_HARD_RESET
> +	bool
> +	default y
> +	depends on BOARD_GIGABYTE_M57SLI
> +
> +config HAVE_HIGH_TABLES
> +	bool
> +	default y
> +	depends on BOARD_GIGABYTE_M57SLI
> +
> +config IOAPIC
> +	bool	
> +	default y
> +	depends on BOARD_GIGABYTE_M57SLI

All "bool"s that are set to y can be written a lot shorter as:

select HAVE_HARD_RESET
select HAVE_HIGH_TABLES
select IOAPIC

above (in the "BOARD_GIGABYTE_GA_M57SLI_S4" section)


> +config LB_CKS_RANGE_START
> +	int
> +	default 49

Not needed, default is 49 already.


> +config MAINBOARD_PART_NUMBER
> +	string
> +	default "m57sli"

	default "GA-M57SLI-S4"


> +	depends on BOARD_GIGABYTE_M57SLI
> +
> +config PCI_64BIT_PREF_MEM
> +	int
> +        default 0
> +	depends on BOARD_GIGABYTE_M57SLI

This is defined bool in src/devices/Kconfig so you can use
"select PCI_64BIT_PREF_MEM".


> +config HAVE_FALLBACK_BOOT
> +	bool
> +	default n
> +	depends on BOARD_GIGABYTE_M57SLI
> +
> +config USE_FALLBACK_IMAGE
> +	bool
> +	default n
> +	depends on BOARD_GIGABYTE_M57SLI

This looks strange. You can probably drop them, but if they stay
HAVE_FALLBACK_BOOT should be y (it's enabled in Options.lb),
not sure about USE_FALLBACK_IMAGE...


> +config HW_MEM_HOLE_SIZEK
> +	hex
> +	default 0x100000
> +	depends on BOARD_GIGABYTE_M57SLI

Hm, not yet defined in kconfig, should probably move somewhere global
(this is work in progress), but I'm not sure.


> +config HAVE_FAILOVER_BOOT
> +	int
> +	default 0
> +	depends on BOARD_GIGABYTE_M57SLI
> +
> +config USE_FAILOVER_IMAGE
> +	int
> +	default 0
> +	depends on BOARD_GIGABYTE_M57SLI

Not sure either, see above.


> +config AP_CODE_IN_CAR
> +	int
> +	default 0
> +	depends on BOARD_GIGABYTE_M57SLI

bool


> +config HW_MEM_HOLE_SIZE_AUTO_INC
> +	int
> +	default 0
> +	depends on BOARD_GIGABYTE_M57SLI

Probably bool.


> +config HT_CHAIN_END_UNITID_BASE
> +	int
> +	default 0
> +	depends on BOARD_GIGABYTE_M57SLI

Looks ok, this is _not_ a bool, AFAIK.


> +config USE_INIT
> +	int
> +	default 0
> +	depends on BOARD_GIGABYTE_M57SLI

bool


> +config SERIAL_CPU_INIT
> +	bool	
> +	default n
> +	depends on BOARD_GIGABYTE_M57SLI

It's actually commented in Options.lb, so the default from
src/config/Options.lb probably is in effect, which is:

define CONFIG_SERIAL_CPU_INIT
        default 1
        export always
        comment "Serialize CPU init"
end

So this should be "select SERIAL_CPU_INIT" I think.


> +config WAIT_BEFORE_CPUS_INIT
> +	int
> +	default 0
> +	depends on BOARD_GIGABYTE_M57SLI

bool


> +config CONSOLE_VGA
> +	bool
> +	default y
> +	depends on BOARD_GIGABYTE_M57SLI
> +
> +config PCI_ROM_RUN
> +	int
> +	default 1
> +	depends on BOARD_GIGABYTE_M57SLI

Both are bool so you can use "select", but these two will probably
be moved to a global place anyway.


> +config K8_REV_F_SUPPORT
> +	hex
> +	default 1
> +	depends on BOARD_GIGABYTE_M57SLI

Probably not needed, the Kconfig file for the CPU socket
sets this one.


> +config FANCTL
> +	int
> +	default 1
> +	depends on BOARD_GIGABYTE_M57SLI

Never defined in kconfig so far, but it should be bool. Also,
you use CONFIG_HAVE_FANCTL below, so it must be named "HAVE_FANCTL"
here.


> +config HAVE_ACPI_TABLES
> +	bool	
> +	default y
> +	depends on BOARD_GIGABYTE_M57SLI

select HAVE_ACPI_TABLES


> Index: src/mainboard/gigabyte/m57sli/devicetree.cb
> ===================================================================
> --- src/mainboard/gigabyte/m57sli/devicetree.cb	(revision 4583)
> +++ src/mainboard/gigabyte/m57sli/devicetree.cb	(working copy)
> @@ -1,202 +1,175 @@
>  chip northbridge/amd/amdk8/root_complex
> -        device apic_cluster 0 on
> -                chip cpu/amd/socket_AM2
> -                        device apic 0 on end
> -                end
> -        end
[...]

The diff for this is very hard to read and has many whitespace changes.
What is it supposed to do? Purely cosmetic changes? Or are there
functional changes in there? Which?


> Index: src/mainboard/gigabyte/Kconfig
> ===================================================================
> --- src/mainboard/gigabyte/Kconfig	(revision 4583)
> +++ src/mainboard/gigabyte/Kconfig	(working copy)
> @@ -1 +1 @@
> -#
> +source "src/mainboard/gigabyte/m57sli/Kconfig" 

This part is correct but some additional stuff is needed, see
asus/Kconfig for an example.


> Index: src/northbridge/amd/amdk8/Makefile.inc
> ===================================================================
> --- src/northbridge/amd/amdk8/Makefile.inc	(revision 4583)
> +++ src/northbridge/amd/amdk8/Makefile.inc	(working copy)
> @@ -1,8 +1,3 @@
> -
> -#default CONFIG_AGP_APERTURE_SIZE=0x4000000
> -#default CONFIG_HAVE_HIGH_TABLES=1
> -
> -

Yep, Makefile.inc is the wrong place. Are they in Kconfig now or
dropped?


Uwe.
Stefan Reinauer - 2009-08-28 19:07:59
On 8/28/09 7:44 PM, Uwe Hermann wrote:

>> +config BOARD_GIGABYTE_M57SLI
>> +	bool "M57SLI"
>>     
> Full names as per vendor website please, in this case:
>
> config BOARD_GIGABYTE_GA_M57SLI_S4
> 	bool "GA-M57SLI-S4"
>
> There are multiple occurences below, please fix them all.
>   

Oh, the convention was actually to use the names of the directories...

Will we have to change them all?

Patch

Index: src/mainboard/gigabyte/m57sli/Kconfig
===================================================================
--- src/mainboard/gigabyte/m57sli/Kconfig	(revision 0)
+++ src/mainboard/gigabyte/m57sli/Kconfig	(revision 0)
@@ -0,0 +1,197 @@ 
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_GIGABYTE
+
+config BOARD_GIGABYTE_M57SLI
+	bool "M57SLI"
+	select ARCH_X86
+	select CPU_AMD_K8
+	select CPU_AMD_SOCKET_AM2
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_NVIDIA_MCP55
+	select SUPERIO_ITE_IT8716F
+	select PIRQ_TABLE
+	select USE_PRINTK_IN_CAR
+	help
+	Gigabyte M57SLI mainboard	
+endchoice
+
+config MAINBOARD_DIR
+	string
+	default gigabyte/m57sli 
+	depends on BOARD_GIGABYTE_M57SLI
+
+config USE_DCACHE_RAM
+	int
+	default 1
+	depends on BOARD_GIGABYTE_M57SLI
+	
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+	depends on BOARD_GIGABYTE_M57SLI
+	
+config DCACHE_RAM_SIZE
+	hex
+	default 0x08000
+	depends on BOARD_GIGABYTE_M57SLI
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+	hex
+	default 0x01000
+	depends on BOARD_GIGABYTE_M57SLI
+
+config APIC_ID_OFFSET
+	int
+	default 16
+	depends on BOARD_GIGABYTE_M57SLI
+
+config HAVE_HARD_RESET
+	bool
+	default y
+	depends on BOARD_GIGABYTE_M57SLI
+
+config HAVE_HIGH_TABLES
+	bool
+	default y
+	depends on BOARD_GIGABYTE_M57SLI
+
+config IOAPIC
+	bool	
+	default y
+	depends on BOARD_GIGABYTE_M57SLI
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 2
+	depends on BOARD_GIGABYTE_M57SLI
+
+config LB_CKS_RANGE_START
+	int
+	default 49
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_GIGABYTE_M57SLI
+
+config LB_CKS_LOC
+	int
+        default 123
+	depends on BOARD_GIGABYTE_M57SLI
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "m57sli"
+	depends on BOARD_GIGABYTE_M57SLI
+
+config PCI_64BIT_PREF_MEM
+	int
+        default 0
+	depends on BOARD_GIGABYTE_M57SLI
+
+config HAVE_FALLBACK_BOOT
+	bool
+	default n
+	depends on BOARD_GIGABYTE_M57SLI
+
+config USE_FALLBACK_IMAGE
+	bool
+	default n
+	depends on BOARD_GIGABYTE_M57SLI
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+	depends on BOARD_GIGABYTE_M57SLI
+
+config MEM_TRAIN_SEQ
+	int
+	default 2
+	depends on BOARD_GIGABYTE_M57SLI
+
+config HAVE_FAILOVER_BOOT
+	int
+	default 0
+	depends on BOARD_GIGABYTE_M57SLI
+
+config USE_FAILOVER_IMAGE
+	int
+	default 0
+	depends on BOARD_GIGABYTE_M57SLI
+
+config MAX_CPUS
+	int
+	default 2
+	depends on BOARD_GIGABYTE_M57SLI
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 1
+	depends on BOARD_GIGABYTE_M57SLI
+
+config AP_CODE_IN_CAR
+	int
+	default 0
+	depends on BOARD_GIGABYTE_M57SLI
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	int
+	default 0
+	depends on BOARD_GIGABYTE_M57SLI
+
+config HT_CHAIN_END_UNITID_BASE
+	int
+	default 0
+	depends on BOARD_GIGABYTE_M57SLI
+
+config USE_INIT
+	int
+	default 0
+	depends on BOARD_GIGABYTE_M57SLI
+
+config SERIAL_CPU_INIT
+	bool	
+	default n
+	depends on BOARD_GIGABYTE_M57SLI
+
+config WAIT_BEFORE_CPUS_INIT
+	int
+	default 0
+	depends on BOARD_GIGABYTE_M57SLI
+
+config CONSOLE_VGA
+	bool
+	default y
+	depends on BOARD_GIGABYTE_M57SLI
+
+config PCI_ROM_RUN
+	int
+	default 1
+	depends on BOARD_GIGABYTE_M57SLI
+
+config K8_REV_F_SUPPORT
+	hex
+	default 1
+	depends on BOARD_GIGABYTE_M57SLI
+
+config FANCTL
+	int
+	default 1
+	depends on BOARD_GIGABYTE_M57SLI
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1022
+	depends on BOARD_GIGABYTE_M57SLI
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x2b80
+	depends on BOARD_GIGABYTE_M57SLI
+
+config HAVE_ACPI_TABLES
+	bool	
+	default y
+	depends on BOARD_GIGABYTE_M57SLI
Index: src/mainboard/gigabyte/m57sli/Makefile.inc
===================================================================
--- src/mainboard/gigabyte/m57sli/Makefile.inc	(revision 0)
+++ src/mainboard/gigabyte/m57sli/Makefile.inc	(revision 0)
@@ -0,0 +1,80 @@ 
+##
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. //TODO: Verify
+## 
+
+driver-y +=  mainboard.o
+
+#needed by irq_tables and mptable and acpi_tables
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_USE_INIT) += cache_as_ram_auto.o
+obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  acpi_tables.o
+obj-$(CONFIG_HAVE_FANCTL) += fanctl.o
+
+#./ssdt.o is in northbridge/amd/amdk8/Config.lb
+
+# This is part of the conversion to init-obj and away from included code. 
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
+
+ifdef POST_EVALUATION
+
+#MAINBOARD_OPTIONS=\
+#	-DCONFIG_AP_IN_SIPI_WAIT=0 \
+#	-DCONFIG_USE_PRINTK_IN_CAR=1 \
+#	-DCONFIG_HAVE_HIGH_TABLES=1
+
+$(obj)/mainboard/$(MAINBOARDDIR)/apc_auto.o: $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c -o $@
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
Index: src/mainboard/gigabyte/m57sli/devicetree.cb
===================================================================
--- src/mainboard/gigabyte/m57sli/devicetree.cb	(revision 4583)
+++ src/mainboard/gigabyte/m57sli/devicetree.cb	(working copy)
@@ -1,202 +1,175 @@ 
 chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_AM2
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8 #mc0
-			device pci 18.0 on 
-				#  devices on link 0, link 0 == LDT 0 
-			        chip southbridge/nvidia/mcp55 
-					device pci 0.0 on end   # HT
-                			device pci 1.0 on # LPC
-						chip superio/ite/it8716f
-							# Floppy and any LDN
-							device pnp 2e.0 off
-                	               			# Watchdog from CLKIN, CLKIN = 24 MHz
-                	                 			irq 0x23 = 0x11 
+	device apic_cluster 0 on
+		chip cpu/amd/socket_AM2
+			device apic 0 on end
+		end
+end
+device pci_domain 0 on
+	chip northbridge/amd/amdk8
+		device pci 18.0 on 
+			chip southbridge/nvidia/mcp55 
+				device pci 0.0 on end
+				device pci 1.0 on
+					chip superio/ite/it8716f
+						# Floppy and any LDN
+						device pnp 2e.0 on
+							# Watchdog from CLKIN, CLKIN = 24 MHz
+							irq 0x23 = 0x11
 							# Serial Flash (SPI only)
-								#0x24 = 0x1a
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.2 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.3 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.4 on #  EC
-                	                 			io 0x60 = 0x290
-                	                 			io 0x62 = 0x230
-                	                			irq 0x70 = 9
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-							end
-                	        			device pnp 2e.6 on #  Mouse
-                	                			irq 0x70 = 12
-							end
-	              	        			device pnp 2e.7 on #  GPIO, SPI flash
-								# pin 84 is not GP10
-								irq 0x25 = 0x0
-				# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
-								irq 0x26 = 0x43
-								# pin 13 is GP35
-								irq 0x27 = 0x20 
-								# pin 70 is not GP46
-								#irq 0x28 = 0x0
-				# pin 6,3,128,127,126 is GP63,64,65,66,67
-								irq 0x29 = 0x81
-				# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
-								#irq 0x2c = 0x1f
-				# Simple I/O base
-								io 0x62 = 0x800
-				# Serial Flash I/O (SPI only)
-								io 0x64 = 0x820
-				# watch dog force timeout (parallel flash only)
-								#irq 0x71 = 0x1
-								# No WDT interrupt
-								irq 0x72 = 0x0 
-					# GPIO pin set 1 disable internal pullup
-								irq 0xb8 = 0x0
-					# GPIO pin set 5 enable internal pullup
-								irq 0xbc = 0x01
-					# SIO pin set 1 alternate function
-								#irq 0xc0 = 0x0
-					# SIO pin set 2 mixed function
-								irq 0xc1 = 0x43
-					# SIO pin set 3 mixed function
-								irq 0xc2 = 0x20
-					# SIO pin set 4 alternate function
-								#irq 0xc3 = 0x0
-					# SIO pin set 1 input mode
-								#irq 0xc8 = 0x0
-					# SIO pin set 2 input mode
-								irq 0xc9 = 0x0
-					# SIO pin set 4 input mode
-								#irq 0xcb = 0x0
-					# Generate SMI# on EC IRQ
-								#irq 0xf0 = 0x10
-					# SMI# level trigger
-								#irq 0xf1 = 0x40
-					# HWMON alert beep pin location
-								irq 0xf6 = 0x28
-							end
-                	        			device pnp 2e.8 off #  MIDI
-								io 0x60 = 0x300
-								irq 0x70 = 10
-							end
-                	        			device pnp 2e.9 off #  GAME
-								io 0x60 = 0x220
-							end
-                	        			device pnp 2e.a off end #  CIR
+							#0x24 = 0x1a
+							io 0x60 = 0x3f0
+							irq 0x70 = 6
+							drq 0x74 = 2
 						end
+						device pnp 2e.1 on # Com1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.2 off # Com2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 2e.3 on #  Parallel Port
+							io 0x60 = 0x378
+							irq 0x70 = 7
+						end
+						device pnp 2e.4 on #  EC
+							io 0x60 = 0x290
+							io 0x62 = 0x230
+							irq 0x70 = 9
+						end
+						device pnp 2e.5 on #  Keyboard
+							io 0x60 = 0x60
+							io 0x62 = 0x64
+							irq 0x70 = 1
+						end
+						device pnp 2e.6 on #  Mouse
+							irq 0x70 = 12
+						end
+						device pnp 2e.7 on #  GPIO, SPI flash
+						# pin 84 is not GP10
+							irq 0x25 = 0x0
+						# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
+							irq 0x26 = 0x43
+						# pin 13 is GP35
+							irq 0x27 = 0x20 
+						# pin 70 is not GP46
+							#irq 0x28 = 0x0
+						# pin 6,3,128,127,126 is GP63,64,65,66,67
+							irq 0x29 = 0x81
+						# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
+							#irq 0x2c = 0x1f
+						# Simple I/O base
+							io 0x62 = 0x800
+						# Serial Flash I/O (SPI only)
+							io 0x64 = 0x820
+						# watch dog force timeout (parallel flash only)
+							#irq 0x71 = 0x1
+						# No WDT interrupt
+							irq 0x72 = 0x0 
+						# GPIO pin set 1 disable internal pullup
+							irq 0xb8 = 0x0
+						# GPIO pin set 5 enable internal pullup
+							irq 0xbc = 0x01
+						# SIO pin set 1 alternate function
+							#irq 0xc0 = 0x0
+						# SIO pin set 2 mixed function
+							irq 0xc1 = 0x43
+						# SIO pin set 3 mixed function
+							irq 0xc2 = 0x20
+						# SIO pin set 4 alternate function
+							#irq 0xc3 = 0x0
+						# SIO pin set 1 input mode
+							#irq 0xc8 = 0x0
+						# SIO pin set 2 input mode
+							irq 0xc9 = 0x0
+						# SIO pin set 4 input mode
+							#irq 0xcb = 0x0
+						# Generate SMI# on EC IRQ
+							#irq 0xf0 = 0x10
+						# SMI# level trigger
+							#irq 0xf1 = 0x40
+						# HWMON alert beep pin location
+							irq 0xf6 = 0x28
+						end
+						device pnp 2e.8 off #  MIDI
+							io 0x60 = 0x300
+							irq 0x70 = 10
+						end
+						device pnp 2e.9 off #  GAME
+							io 0x60 = 0x220
+						end
+						device pnp 2e.a off #  CIR
+						end
 					end
-			                device pci 1.1 on # SM 0
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end  
-                                                end              
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 0-1-0
-                                                        device i2c 52 on end
-                                                end             
-                                                chip drivers/generic/generic #dimm 0-1-1
-                                                        device i2c 53 on end
-                                                end              
-                                                chip drivers/generic/generic #dimm 1-0-0
-                                                        device i2c 54 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-0-1
-                                                        device i2c 55 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-0
-                                                        device i2c 56 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-1
-                                                        device i2c 57 on end
-                                                end 
-					end # SM
-#WTF?!? We already have device pci 1.1 in the section above
-                                        device pci 1.1 on # SM 1
-#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#                                                chip drivers/generic/generic #PCIXA Slot1
-#                                                        device i2c 50 on end
-#                                                end
-#                                                chip drivers/generic/generic #PCIXB Slot1
-#                                                        device i2c 51 on end
-#                                                end     
-#                                                chip drivers/generic/generic #PCIXB Slot2
-#                                                        device i2c 52 on end
-#                                                end             
-#                                                chip drivers/generic/generic #PCI Slot1
-#                                                        device i2c 53 on end
-#                                                end              
-#                                                chip drivers/generic/generic #Master MCP55 PCI-E
-#                                                        device i2c 54 on end
-#                                                end     
-#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
-#                                                        device i2c 55 on end
-#                                                end             
-                                                chip drivers/generic/generic #MAC EEPROM
-                                                        device i2c 51 on end
-                                                end 
-
-                                        end # SM 
-	                		device pci 2.0 on end # USB 1.1
-        	        		device pci 2.1 on end # USB 2
-                			device pci 4.0 on end # IDE
-	                		device pci 5.0 on end # SATA 0
-	                		device pci 5.1 on end # SATA 1
-	                		device pci 5.2 on end # SATA 2
-                			device pci 6.0 on end # PCI
-        	        		device pci 6.1 on end # AZA
-	                		device pci 8.0 on end # NIC
-	                		device pci 9.0 off end # NIC
-        	       			device pci a.0 on end # PCI E 5
-        	       			device pci b.0 on end # PCI E 4
-                			device pci c.0 on end # PCI E 3
-                			device pci d.0 on end # PCI E 2
-                			device pci e.0 on end # PCI E 1
-        	       			device pci f.0 on end # PCI E 0
-	                                register "ide0_enable" = "1"
-                	                register "sata0_enable" = "1"
-                        	        register "sata1_enable" = "1"
+				end
+				device pci 1.1 on
+					chip drivers/generic/generic #dimm 0-0-0
+						device i2c 50 on end
+					end
+					chip drivers/generic/generic #dimm 0-0-1
+						device i2c 51 on end
+					end
+					chip drivers/generic/generic #dimm 0-1-0
+						device i2c 52 on end
+					end
+					chip drivers/generic/generic #dimm 0-1-1
+						device i2c 53 on end
+					end
+					chip drivers/generic/generic #dimm 1-0-0
+						device i2c 54 on end
+					end
+					chip drivers/generic/generic #dimm 1-0-1
+						device i2c 55 on end
+					end
+					chip drivers/generic/generic #dimm 1-1-0
+						device i2c 56 on end
+					end
+					chip drivers/generic/generic #dimm 1-1-1
+						device i2c 57 on end
+					end
+				end # SM
+	                	device pci 2.0 on end # USB 1.1
+        	        	device pci 2.1 on end # USB 2
+                		device pci 4.0 on end # IDE
+	                	device pci 5.0 on end # SATA 0
+	                	device pci 5.1 on end # SATA 1
+	                	device pci 5.2 on end # SATA 2
+                		device pci 6.0 on end # PCI
+        	        	device pci 6.1 on end # AUDIO
+	                	device pci 8.0 on end # NIC
+	                	device pci 9.0 off end # N/A
+        	       		device pci a.0 on end # PCI E 5
+        	       		device pci b.0 on end # PCI E 4
+                		device pci c.0 on end # PCI E 3
+                		device pci d.0 on end # PCI E 2
+                		device pci e.0 on end # PCI E 1
+        	       		device pci f.0 on end # PCI E 0
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "sata1_enable" = "1"
 					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" = "0x51"
 				end
-			end #  device pci 18.0 
+			end #device pci 18.0
 			device pci 18.0 on end # Link 1
-			device pci 18.0 on end
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
 		end # mc0
-		
 	end # PCI domain
-	
-#       chip drivers/generic/debug 
-#               device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 on end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 on end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#               device pnp 0.7 off end # tsc
-#                device pnp 0.8 off  end # io
-#                device pnp 0.9 off end # io
-#       end  
+
+#	 chip drivers/generic/debug 
+#		device pnp 0.0 off end # chip name
+#		device pnp 0.1 on end # pci_regs_all
+#		device pnp 0.2 on end # mem
+#		device pnp 0.3 off end # cpuid
+#		device pnp 0.4 on end # smbus_regs_all
+#		device pnp 0.5 off end # dual core msr
+#		device pnp 0.6 off end # cache size
+#		device pnp 0.7 off end # tsc
+#		device pnp 0.8 off  end # io
+#		device pnp 0.9 off end # io
+#	 end  
+
 end #root_complex
Index: src/mainboard/gigabyte/Kconfig
===================================================================
--- src/mainboard/gigabyte/Kconfig	(revision 4583)
+++ src/mainboard/gigabyte/Kconfig	(working copy)
@@ -1 +1 @@ 
-#
+source "src/mainboard/gigabyte/m57sli/Kconfig" 
Index: src/northbridge/amd/amdk8/Makefile.inc
===================================================================
--- src/northbridge/amd/amdk8/Makefile.inc	(revision 4583)
+++ src/northbridge/amd/amdk8/Makefile.inc	(working copy)
@@ -1,8 +1,3 @@ 
-
-#default CONFIG_AGP_APERTURE_SIZE=0x4000000
-#default CONFIG_HAVE_HIGH_TABLES=1
-
-
 driver-y += northbridge.o
 driver-y += misc_control.o
 obj-y += get_sblk_pci1234.o