Patchwork Streamline CPU_ADDR_BITS usage

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Submitter Uwe Hermann
Date 2010-10-03 18:47:35
Message ID <20101003184734.GF3256@greenwood>
Download mbox | patch
Permalink /patch/2029/
State Superseded
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Comments

Uwe Hermann - 2010-10-03 18:47:35
See patch.


Uwe.
Patrick Georgi - 2010-10-03 19:18:25
Am 03.10.2010 20:47, schrieb Uwe Hermann:
> -	movl	$0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
> -	jmp_if_k8(wbcache_post_fam10_setup)
> -	movl	$0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
> -wbcache_post_fam10_setup:
> +	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
This was to allow a single image to run through CAR with both K8 and
Fam10. I suppose that's not necessary anymore, given that the bootblock
doesn't use CAR, and any chip selection can and should happen there.

So I think it's safe to go ahead with that one - just stating since
you're seriously changing behaviour here.


Patrick
Carl-Daniel Hailfinger - 2010-10-03 21:04:32
On 03.10.2010 21:18, Patrick Georgi wrote:
> Am 03.10.2010 20:47, schrieb Uwe Hermann:
>   
>> -	movl	$0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
>> -	jmp_if_k8(wbcache_post_fam10_setup)
>> -	movl	$0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
>> -wbcache_post_fam10_setup:
>> +	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
>>     
> This was to allow a single image to run through CAR with both K8 and
> Fam10. I suppose that's not necessary anymore, given that the bootblock
> doesn't use CAR, and any chip selection can and should happen there.
>   

I want to be able to use my socket AM2+ board with K8 and Fam10
processors. If I also want fallback/normal images, this change forces me
to use 4 images instead of 2. And yes, people who use mainboards
actually may expect to be able to use processors from different
generations if the "normal" BIOS can handle that as well.
Due to that, I'd say Nack, but if you have strong technical reasons
(instead of cosmetic reasons) which result in a net benefit to end users
even if you factor in the feature loss, I will retract the Nack.

Regards,
Carl-Daniel
Patrick Georgi - 2010-10-03 21:07:27
Am 03.10.2010 23:04, schrieb Carl-Daniel Hailfinger:
> I want to be able to use my socket AM2+ board with K8 and Fam10
> processors. If I also want fallback/normal images, this change forces me
> to use 4 images instead of 2. And yes, people who use mainboards
> actually may expect to be able to use processors from different
> generations if the "normal" BIOS can handle that as well.
> Due to that, I'd say Nack, but if you have strong technical reasons
> (instead of cosmetic reasons) which result in a net benefit to end users
> even if you factor in the feature loss, I will retract the Nack.
You're still required to have an image for K8 and Fam10 each, simply
because we don't support runtime selection of northbridge code in the
romstage.

The only thing I worked on was getting through CAR on either CPU, then
jumped into the "right" image right afterwards (as was usual in pre-CBFS
images)

So we can debate if we want to keep the current support, but that
requires more work (architecture changes in coreboot) to support
multiple northbridges in all places, not just CAR.


Patrick

Patch

Streamline CPU_ADDR_BITS usage.

Let CPUs 'select' the proper kconfig variable which defines the number
of address space bits supported by the respective CPU.

This value is now used (directly or indirectly) in multiple places instead
of hardcoding the values multiple times, risking inconsistencies:

 - x86_setup_mtrrs() now uses CONFIG_CPU_ADDR_BITS directly, no need to
   pass it in as parameter.

 - amd_setup_mtrrs() can thus also be simplified.

 - src/cpu/amd/car/cache_as_ram.inc can be simplified too.

 - Derived from CONFIG_CPU_ADDR_BITS we now also have
   CONFIG_CPU_ADDR_BITS_MASK, which is used in CAR files for
   MTRRphysMask_MSR settings.

 - As an additional benefit, this also makes the model_6ex and model_6fx
   CAR implementations identical. This will be refactored in a follow-up patch.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>

Index: src/Kconfig
===================================================================
--- src/Kconfig	(Revision 5908)
+++ src/Kconfig	(Arbeitskopie)
@@ -134,10 +134,40 @@ 
 	hex
 	default 0x0
 
+# These define how many address space bits a CPU supports. The CPU's Kconfig
+# file should 'select' the correct one (otherwise 36bits is the default).
+config CPU_ADDR_BITS_32
+	def_bool n
+
+config CPU_ADDR_BITS_36
+	def_bool y
+
+config CPU_ADDR_BITS_40
+	def_bool n
+
+config CPU_ADDR_BITS_48
+	def_bool n
+
 config CPU_ADDR_BITS
 	int
-	default 36
+	default 32 if CPU_ADDR_BITS_32
+	default 36 if CPU_ADDR_BITS_36
+	default 40 if CPU_ADDR_BITS_40
+	default 48 if CPU_ADDR_BITS_48
+	help
+	  Map the bools to an int (the number of the CPU's address space bits).
 
+config CPU_ADDR_BITS_MASK
+	hex
+	default 0x00000000 if CPU_ADDR_BITS_32
+	default 0x0000000f if CPU_ADDR_BITS_36
+	default 0x000000ff if CPU_ADDR_BITS_40
+	default 0x0000ffff if CPU_ADDR_BITS_48
+	help
+	  Map the number of address space bits supported by the CPU to the
+	  mask field value as it needs to be written into the upper 32 bits
+	  of the various MTRRphysMask_MSR MSRs.
+
 config LOGICAL_CPUS
 	bool
 	default y
Index: src/include/cpu/x86/mtrr.h
===================================================================
--- src/include/cpu/x86/mtrr.h	(Revision 5908)
+++ src/include/cpu/x86/mtrr.h	(Arbeitskopie)
@@ -37,8 +37,8 @@ 
 #if !defined (ASSEMBLY) && !defined(__PRE_RAM__)
 #include <device/device.h>
 void enable_fixed_mtrr(void);
-void x86_setup_var_mtrrs(unsigned address_bits);
-void x86_setup_mtrrs(unsigned address_bits);
+void x86_setup_var_mtrrs(void);
+void x86_setup_mtrrs(void);
 int x86_mtrr_check(void);
 void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
 void x86_setup_fixed_mtrrs(void);
Index: src/cpu/via/model_c3/Kconfig
===================================================================
--- src/cpu/via/model_c3/Kconfig	(Revision 5908)
+++ src/cpu/via/model_c3/Kconfig	(Arbeitskopie)
@@ -2,3 +2,4 @@ 
 	bool
 	select UDELAY_TSC
 	select MMX
+	select CPU_ADDR_BITS_36
Index: src/cpu/via/model_c3/model_c3_init.c
===================================================================
--- src/cpu/via/model_c3/model_c3_init.c	(Revision 5908)
+++ src/cpu/via/model_c3/model_c3_init.c	(Arbeitskopie)
@@ -30,7 +30,7 @@ 
 static void model_c3_init(device_t dev)
 {
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
Index: src/cpu/via/model_c7/Kconfig
===================================================================
--- src/cpu/via/model_c7/Kconfig	(Revision 5908)
+++ src/cpu/via/model_c7/Kconfig	(Arbeitskopie)
@@ -9,6 +9,7 @@ 
 	select MMX
 	select SSE2
 	select CACHE_AS_RAM
+	select CPU_ADDR_BITS_36
 
 config DCACHE_RAM_BASE
 	hex
Index: src/cpu/via/model_c7/model_c7_init.c
===================================================================
--- src/cpu/via/model_c7/model_c7_init.c	(Revision 5908)
+++ src/cpu/via/model_c7/model_c7_init.c	(Arbeitskopie)
@@ -204,7 +204,7 @@ 
 	x86_enable_cache();
 
 	/* Set up Memory Type Range Registers */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
Index: src/cpu/amd/socket_S1G1/Kconfig
===================================================================
--- src/cpu/amd/socket_S1G1/Kconfig	(Revision 5908)
+++ src/cpu/amd/socket_S1G1/Kconfig	(Arbeitskopie)
@@ -8,6 +8,7 @@ 
 	select K8_REV_F_SUPPORT
 	select K8_HT_FREQ_1G_SUPPORT
 	select CPU_AMD_MODEL_FXX
+	select CPU_ADDR_BITS_40
 
 config CPU_SOCKET_TYPE
 	hex
@@ -18,10 +19,6 @@ 
 	hex
 	default 0x0204
 
-config CPU_ADDR_BITS
-	int
-	default 40
-
 config DCACHE_RAM_BASE
 	hex
 	default 0xc8000
Index: src/cpu/amd/mtrr/amd_mtrr.c
===================================================================
--- src/cpu/amd/mtrr/amd_mtrr.c	(Revision 5908)
+++ src/cpu/amd/mtrr/amd_mtrr.c	(Arbeitskopie)
@@ -103,7 +103,6 @@ 
 
 void amd_setup_mtrrs(void)
 {
-	unsigned long address_bits;
 	struct mem_state state;
 	unsigned long i;
 	msr_t msr;
@@ -175,13 +174,8 @@ 
 
 	enable_cache();
 
-	/* FIXME we should probably query the cpu for this
-	 * but so far this is all any recent AMD cpu has supported.
-	 */
-	address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
-
 	/* Now that I have mapped what is memory and what is not
 	 * Setup the mtrrs so we can cache the memory.
 	 */
-	x86_setup_var_mtrrs(address_bits);
+	x86_setup_var_mtrrs();
 }
Index: src/cpu/amd/socket_940/Kconfig
===================================================================
--- src/cpu/amd/socket_940/Kconfig	(Revision 5908)
+++ src/cpu/amd/socket_940/Kconfig	(Arbeitskopie)
@@ -8,6 +8,7 @@ 
 	select K8_HT_FREQ_1G_SUPPORT
 	select CPU_AMD_MODEL_FXX
 	select CACHE_AS_RAM
+	select CPU_ADDR_BITS_40
 
 config CPU_SOCKET_TYPE
 	hex
@@ -17,10 +18,6 @@ 
 	hex
 	default 0x108
 
-config CPU_ADDR_BITS
-	int
-	default 40
-
 config DCACHE_RAM_BASE
 	hex
 	default 0xc8000
Index: src/cpu/amd/car/cache_as_ram.inc
===================================================================
--- src/cpu/amd/car/cache_as_ram.inc	(Revision 5908)
+++ src/cpu/amd/car/cache_as_ram.inc	(Arbeitskopie)
@@ -279,10 +279,7 @@ 
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
-	jmp_if_k8(wbcache_post_fam10_setup)
-	movl	$0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
-wbcache_post_fam10_setup:
+	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
Index: src/cpu/amd/model_10xxx/Kconfig
===================================================================
--- src/cpu/amd/model_10xxx/Kconfig	(Revision 5908)
+++ src/cpu/amd/model_10xxx/Kconfig	(Arbeitskopie)
@@ -3,12 +3,8 @@ 
 	select CACHE_AS_RAM
 	select SSE
 	select SSE2
+	select CPU_ADDR_BITS_48
 
-config CPU_ADDR_BITS
-	int
-	default 48
-	depends on CPU_AMD_MODEL_10XXX
-
 config DCACHE_RAM_BASE
 	hex
 	default 0xc4000
Index: src/cpu/x86/mtrr/mtrr.c
===================================================================
--- src/cpu/x86/mtrr/mtrr.c	(Revision 5908)
+++ src/cpu/x86/mtrr/mtrr.c	(Arbeitskopie)
@@ -388,13 +388,14 @@ 
 
 }
 
-void x86_setup_var_mtrrs(unsigned address_bits)
-/* this routine needs to know how many address bits a given processor
- * supports.  CPUs get grumpy when you set too many bits in
- * their mtrr registers :(  I would generically call cpuid here
- * and find out how many physically supported but some cpus are
- * buggy, and report more bits then they actually support.
+/*
+ * This routine needs to know how many address bits a given processor supports
+ * (CONFIG_CPU_ADDR_BITS). CPUs get grumpy when you set too many bits in
+ * their MTRR registers. We could generically use CPUID here and find out how
+ * many are physically supported, but some CPUs are buggy, and report more
+ * bits than they actually support.
  */
+void x86_setup_var_mtrrs(void)
 {
 	/* Try this the simple way of incrementally adding together
 	 * mtrrs.  If this doesn't work out we can get smart again
@@ -413,7 +414,7 @@ 
 	var_state.hole_sizek = 0;
 #endif
 	var_state.reg = 0;
-	var_state.address_bits = address_bits;
+	var_state.address_bits = CONFIG_CPU_ADDR_BITS;
 
 	search_global_resources(
 		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
@@ -449,10 +450,10 @@ 
 	post_code(0x6A);
 }
 
-void x86_setup_mtrrs(unsigned address_bits)
+void x86_setup_mtrrs(void)
 {
 	x86_setup_fixed_mtrrs();
-	x86_setup_var_mtrrs(address_bits);
+	x86_setup_var_mtrrs();
 }
 
 
Index: src/cpu/intel/model_f3x/Kconfig
===================================================================
--- src/cpu/intel/model_f3x/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_f3x/Kconfig	(Arbeitskopie)
@@ -1,3 +1,4 @@ 
 config CPU_INTEL_MODEL_F3X
 	bool
 	select SMP
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/model_f3x/model_f3x_init.c
===================================================================
--- src/cpu/intel/model_f3x/model_f3x_init.c	(Revision 5908)
+++ src/cpu/intel/model_f3x/model_f3x_init.c	(Arbeitskopie)
@@ -34,7 +34,7 @@ 
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
Index: src/cpu/intel/ep80579/Kconfig
===================================================================
--- src/cpu/intel/ep80579/Kconfig	(Revision 5908)
+++ src/cpu/intel/ep80579/Kconfig	(Arbeitskopie)
@@ -1,3 +1,4 @@ 
 config CPU_INTEL_EP80579
 	bool
 	select SSE
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/ep80579/ep80579_init.c
===================================================================
--- src/cpu/intel/ep80579/ep80579_init.c	(Revision 5908)
+++ src/cpu/intel/ep80579/ep80579_init.c	(Arbeitskopie)
@@ -41,7 +41,7 @@ 
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
Index: src/cpu/intel/model_6ex/Kconfig
===================================================================
--- src/cpu/intel/model_6ex/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_6ex/Kconfig	(Arbeitskopie)
@@ -4,3 +4,4 @@ 
 	select SSE2
 	select UDELAY_LAPIC
 	select AP_IN_SIPI_WAIT
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/model_6ex/model_6ex_init.c
===================================================================
--- src/cpu/intel/model_6ex/model_6ex_init.c	(Revision 5908)
+++ src/cpu/intel/model_6ex/model_6ex_init.c	(Arbeitskopie)
@@ -179,7 +179,7 @@ 
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
Index: src/cpu/intel/model_6ex/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram.inc	(Revision 5908)
+++ src/cpu/intel/model_6ex/cache_as_ram.inc	(Arbeitskopie)
@@ -63,7 +63,7 @@ 
 	/* Set Cache-as-RAM mask. */
 	movl	$(MTRRphysMask_MSR(0)), %ecx
 	movl	$(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
-	movl	$0x0000000f, %edx
+	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
 	wrmsr
 
 	enable_mtrr()
@@ -107,7 +107,7 @@ 
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$0x0000000f, %edx
+	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
@@ -176,7 +176,7 @@ 
 	wrmsr
 	movl	$MTRRphysMask_MSR(0), %ecx
 	movl	$(~(1024 * 1024 - 1) | (1 << 11)), %eax
-	movl	$0x0000000f, %edx	// 36bit address space
+	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
 	wrmsr
 
 	post_code(0x39)
Index: src/cpu/intel/car/cache_as_ram.inc
===================================================================
--- src/cpu/intel/car/cache_as_ram.inc	(Revision 5908)
+++ src/cpu/intel/car/cache_as_ram.inc	(Arbeitskopie)
@@ -231,7 +231,7 @@ 
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$0x0000000f, %edx
+	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
Index: src/cpu/intel/model_69x/Kconfig
===================================================================
--- src/cpu/intel/model_69x/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_69x/Kconfig	(Arbeitskopie)
@@ -1,3 +1,4 @@ 
 config CPU_INTEL_MODEL_69X
 	bool
 	select SMP
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/model_69x/model_69x_init.c
===================================================================
--- src/cpu/intel/model_69x/model_69x_init.c	(Revision 5908)
+++ src/cpu/intel/model_69x/model_69x_init.c	(Arbeitskopie)
@@ -24,7 +24,7 @@ 
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
Index: src/cpu/intel/model_f0x/Kconfig
===================================================================
--- src/cpu/intel/model_f0x/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_f0x/Kconfig	(Arbeitskopie)
@@ -1,3 +1,4 @@ 
 config CPU_INTEL_MODEL_F0X
 	bool
 	select SMP
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/model_f0x/model_f0x_init.c
===================================================================
--- src/cpu/intel/model_f0x/model_f0x_init.c	(Revision 5908)
+++ src/cpu/intel/model_f0x/model_f0x_init.c	(Arbeitskopie)
@@ -30,7 +30,7 @@ 
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
Index: src/cpu/intel/model_6bx/Kconfig
===================================================================
--- src/cpu/intel/model_6bx/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_6bx/Kconfig	(Arbeitskopie)
@@ -1,3 +1,4 @@ 
 config CPU_INTEL_MODEL_6BX
 	bool
 	select SMP
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/model_6bx/model_6bx_init.c
===================================================================
--- src/cpu/intel/model_6bx/model_6bx_init.c	(Revision 5908)
+++ src/cpu/intel/model_6bx/model_6bx_init.c	(Arbeitskopie)
@@ -71,7 +71,7 @@ 
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
Index: src/cpu/intel/model_f2x/Kconfig
===================================================================
--- src/cpu/intel/model_f2x/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_f2x/Kconfig	(Arbeitskopie)
@@ -1,3 +1,4 @@ 
 config CPU_INTEL_MODEL_F2X
 	bool
 	select SMP
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/model_f2x/model_f2x_init.c
===================================================================
--- src/cpu/intel/model_f2x/model_f2x_init.c	(Revision 5908)
+++ src/cpu/intel/model_f2x/model_f2x_init.c	(Arbeitskopie)
@@ -33,7 +33,7 @@ 
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
Index: src/cpu/intel/model_6dx/Kconfig
===================================================================
--- src/cpu/intel/model_6dx/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_6dx/Kconfig	(Arbeitskopie)
@@ -1,3 +1,4 @@ 
 config CPU_INTEL_MODEL_6DX
 	bool
 	select SMP
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/model_6dx/model_6dx_init.c
===================================================================
--- src/cpu/intel/model_6dx/model_6dx_init.c	(Revision 5908)
+++ src/cpu/intel/model_6dx/model_6dx_init.c	(Arbeitskopie)
@@ -24,7 +24,7 @@ 
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
Index: src/cpu/intel/model_106cx/Kconfig
===================================================================
--- src/cpu/intel/model_106cx/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_106cx/Kconfig	(Arbeitskopie)
@@ -4,3 +4,4 @@ 
 	select SSE2
 	select UDELAY_LAPIC
 	select AP_IN_SIPI_WAIT
+	select CPU_ADDR_BITS_32
Index: src/cpu/intel/model_106cx/model_106cx_init.c
===================================================================
--- src/cpu/intel/model_106cx/model_106cx_init.c	(Revision 5908)
+++ src/cpu/intel/model_106cx/model_106cx_init.c	(Arbeitskopie)
@@ -157,7 +157,7 @@ 
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(32);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
Index: src/cpu/intel/model_106cx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram.inc	(Revision 5908)
+++ src/cpu/intel/model_106cx/cache_as_ram.inc	(Arbeitskopie)
@@ -63,7 +63,7 @@ 
 	/* Set Cache-as-RAM mask. */
 	movl	$(MTRRphysMask_MSR(0)), %ecx
 	movl	$(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
-	xorl	%edx, %edx
+	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
 	wrmsr
 
 	enable_mtrr()
@@ -107,7 +107,7 @@ 
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
-	xorl	%edx, %edx
+	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
@@ -176,7 +176,7 @@ 
 	wrmsr
 	movl	$MTRRphysMask_MSR(0), %ecx
 	movl	$(~(1024 * 1024 - 1) | (1 << 11)), %eax
-	xorl	%edx, %edx
+	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
 	wrmsr
 
 	post_code(0x39)
Index: src/cpu/intel/model_f4x/Kconfig
===================================================================
--- src/cpu/intel/model_f4x/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_f4x/Kconfig	(Arbeitskopie)
@@ -1,3 +1,4 @@ 
 config CPU_INTEL_MODEL_F4X
 	bool
 	select SMP
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/model_f4x/model_f4x_init.c
===================================================================
--- src/cpu/intel/model_f4x/model_f4x_init.c	(Revision 5908)
+++ src/cpu/intel/model_f4x/model_f4x_init.c	(Arbeitskopie)
@@ -31,7 +31,7 @@ 
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
Index: src/cpu/intel/model_6fx/Kconfig
===================================================================
--- src/cpu/intel/model_6fx/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_6fx/Kconfig	(Arbeitskopie)
@@ -4,3 +4,4 @@ 
 	select SSE2
 	select UDELAY_LAPIC
 	select AP_IN_SIPI_WAIT
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/model_6fx/model_6fx_init.c
===================================================================
--- src/cpu/intel/model_6fx/model_6fx_init.c	(Revision 5908)
+++ src/cpu/intel/model_6fx/model_6fx_init.c	(Arbeitskopie)
@@ -206,7 +206,7 @@ 
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Setup Page Attribute Tables (PAT) */
Index: src/cpu/intel/model_6fx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram.inc	(Revision 5908)
+++ src/cpu/intel/model_6fx/cache_as_ram.inc	(Arbeitskopie)
@@ -70,7 +70,7 @@ 
 	/* Set Cache-as-RAM mask. */
 	movl	$(MTRRphysMask_MSR(0)), %ecx
 	movl	$(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
-	movl	$0x0000000f, %edx
+	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
 	wrmsr
 
 	enable_mtrr()
@@ -114,7 +114,7 @@ 
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$0x0000000f, %edx
+	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
@@ -183,7 +183,7 @@ 
 	wrmsr
 	movl	$MTRRphysMask_MSR(0), %ecx
 	movl	$(~(1024 * 1024 - 1) | (1 << 11)), %eax
-	movl	$0x0000000f, %edx	// 36bit address space
+	movl	$CONFIG_CPU_ADDR_BITS_MASK, %edx
 	wrmsr
 
 	post_code(0x39)
Index: src/cpu/intel/model_6xx/Kconfig
===================================================================
--- src/cpu/intel/model_6xx/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_6xx/Kconfig	(Arbeitskopie)
@@ -1,3 +1,4 @@ 
 config CPU_INTEL_MODEL_6XX
 	bool
 	select SMP
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/model_6xx/model_6xx_init.c
===================================================================
--- src/cpu/intel/model_6xx/model_6xx_init.c	(Revision 5908)
+++ src/cpu/intel/model_6xx/model_6xx_init.c	(Arbeitskopie)
@@ -38,7 +38,7 @@ 
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
Index: src/cpu/intel/model_68x/Kconfig
===================================================================
--- src/cpu/intel/model_68x/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_68x/Kconfig	(Arbeitskopie)
@@ -21,3 +21,4 @@ 
 config CPU_INTEL_MODEL_68X
 	bool
 	select SMP
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/model_68x/model_68x_init.c
===================================================================
--- src/cpu/intel/model_68x/model_68x_init.c	(Revision 5908)
+++ src/cpu/intel/model_68x/model_68x_init.c	(Arbeitskopie)
@@ -85,7 +85,7 @@ 
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
Index: src/cpu/intel/model_1067x/Kconfig
===================================================================
--- src/cpu/intel/model_1067x/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_1067x/Kconfig	(Arbeitskopie)
@@ -2,3 +2,4 @@ 
 	bool
 	select SMP
 	select SSE2
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/model_1067x/model_1067x_init.c
===================================================================
--- src/cpu/intel/model_1067x/model_1067x_init.c	(Revision 5908)
+++ src/cpu/intel/model_1067x/model_1067x_init.c	(Arbeitskopie)
@@ -189,7 +189,7 @@ 
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
Index: src/cpu/intel/model_f1x/Kconfig
===================================================================
--- src/cpu/intel/model_f1x/Kconfig	(Revision 5908)
+++ src/cpu/intel/model_f1x/Kconfig	(Arbeitskopie)
@@ -1,3 +1,4 @@ 
 config CPU_INTEL_MODEL_F1X
 	bool
 	select SMP
+	select CPU_ADDR_BITS_36
Index: src/cpu/intel/model_f1x/model_f1x_init.c
===================================================================
--- src/cpu/intel/model_f1x/model_f1x_init.c	(Revision 5908)
+++ src/cpu/intel/model_f1x/model_f1x_init.c	(Arbeitskopie)
@@ -30,7 +30,7 @@ 
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */