From patchwork Mon Oct 4 15:48:03 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: First attempt at eliminating #include *.c Date: Mon, 04 Oct 2010 15:48:03 -0000 From: Patrick Georgi X-Patchwork-Id: 2035 Message-Id: <4CA9F733.9050908@georgi-clan.de> To: coreboot@coreboot.org Hi, attached patch removes several "#include *.c" from romstage.c in i945 based boards and moves those files to romstage-srcs instead (ie. separate compilation units). There's one global change, the removal of ramtest.c from CAR romstage.cs It's abuild tested and boot tested on kontron/986lcd-m. Probably should be tested (so that ramtest.c stuff is a separate patch), but the global changes were actually the last change I made. Signed-off-by: Patrick Georgi Acked-by: Uwe Hermann Index: src/southbridge/intel/i82801gx/i82801gx_early_smbus.c =================================================================== --- src/southbridge/intel/i82801gx/i82801gx_early_smbus.c (revision 5908) +++ src/southbridge/intel/i82801gx/i82801gx_early_smbus.c (working copy) @@ -18,11 +18,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include +#include +#include #include +#include #include "i82801gx.h" #include "i82801gx_smbus.h" -static void enable_smbus(void) +int smbus_read_byte(unsigned device, unsigned address); + +void enable_smbus(void) { device_t dev; @@ -52,7 +58,7 @@ print_debug("SMBus controller enabled.\n"); } -static inline int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } Index: src/southbridge/intel/i82801gx/Makefile.inc =================================================================== --- src/southbridge/intel/i82801gx/Makefile.inc (revision 5908) +++ src/southbridge/intel/i82801gx/Makefile.inc (working copy) @@ -35,3 +35,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smihandler.c + +romstage-y += i82801gx_early_smbus.c +romstage-$(CONFIG_USBDEBUG) += i82801gx_usb_debug.c + Index: src/southbridge/intel/i82801gx/i82801gx_smbus.h =================================================================== --- src/southbridge/intel/i82801gx/i82801gx_smbus.h (revision 5908) +++ src/southbridge/intel/i82801gx/i82801gx_smbus.h (working copy) @@ -20,6 +20,8 @@ #include +void enable_smbus(void); + static void smbus_delay(void) { inb(0x80); Index: src/mainboard/iwill/dk8_htx/romstage.c =================================================================== --- src/mainboard/iwill/dk8_htx/romstage.c (revision 5908) +++ src/mainboard/iwill/dk8_htx/romstage.c (working copy) @@ -91,7 +91,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "lib/ramtest.c" /* tyan does not want the default */ #include "resourcemap.c" Index: src/mainboard/iwill/dk8s2/romstage.c =================================================================== --- src/mainboard/iwill/dk8s2/romstage.c (revision 5908) +++ src/mainboard/iwill/dk8s2/romstage.c (working copy) @@ -91,7 +91,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "lib/ramtest.c" /* tyan does not want the default */ #include "northbridge/amd/amdk8/resourcemap.c" Index: src/mainboard/iwill/dk8x/romstage.c =================================================================== --- src/mainboard/iwill/dk8x/romstage.c (revision 5908) +++ src/mainboard/iwill/dk8x/romstage.c (working copy) @@ -91,7 +91,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "lib/ramtest.c" /* tyan does not want the default */ #include "northbridge/amd/amdk8/resourcemap.c" Index: src/mainboard/bcom/winnetp680/romstage.c =================================================================== --- src/mainboard/bcom/winnetp680/romstage.c (revision 5908) +++ src/mainboard/bcom/winnetp680/romstage.c (working copy) @@ -27,11 +27,11 @@ #include #include #include -#include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" +#include #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/winbond/w83697hf/w83697hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) Index: src/mainboard/getac/p470/romstage.c =================================================================== --- src/mainboard/getac/p470/romstage.c (revision 5908) +++ src/mainboard/getac/p470/romstage.c (working copy) @@ -26,24 +26,20 @@ #include #include #include +#include #include #include #include -#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "southbridge/intel/i82801gx/i82801gx.h" -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" +void enable_smbus(void); -#include "northbridge/intel/i945/udelay.c" - -#include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) +void setup_ich7_gpios(void) { u32 gpios; @@ -87,18 +83,6 @@ outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ } -#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ Index: src/mainboard/broadcom/blast/romstage.c =================================================================== --- src/mainboard/broadcom/blast/romstage.c (revision 5908) +++ src/mainboard/broadcom/blast/romstage.c (working copy) @@ -13,7 +13,6 @@ #include #include #include -#include "lib/ramtest.c" #include #include "northbridge/amd/amdk8/incoherent_ht.c" Index: src/mainboard/thomson/ip1000/romstage.c =================================================================== --- src/mainboard/thomson/ip1000/romstage.c (revision 5908) +++ src/mainboard/thomson/ip1000/romstage.c (working copy) @@ -28,7 +28,7 @@ #include #include "pc80/udelay_io.c" #include -#include "lib/ramtest.c" +#include #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" Index: src/mainboard/wyse/s50/romstage.c =================================================================== --- src/mainboard/wyse/s50/romstage.c (revision 5908) +++ src/mainboard/wyse/s50/romstage.c (working copy) @@ -25,7 +25,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/supermicro/h8dmr/romstage.c =================================================================== --- src/mainboard/supermicro/h8dmr/romstage.c (revision 5908) +++ src/mainboard/supermicro/h8dmr/romstage.c (working copy) @@ -49,7 +49,7 @@ #include #include -#include "lib/ramtest.c" +#include #include Index: src/mainboard/supermicro/h8dme/romstage.c =================================================================== --- src/mainboard/supermicro/h8dme/romstage.c (revision 5908) +++ src/mainboard/supermicro/h8dme/romstage.c (working copy) @@ -46,7 +46,7 @@ #include #include -#include "lib/ramtest.c" +#include #include Index: src/mainboard/supermicro/h8dmr_fam10/romstage.c =================================================================== --- src/mainboard/supermicro/h8dmr_fam10/romstage.c (revision 5908) +++ src/mainboard/supermicro/h8dmr_fam10/romstage.c (working copy) @@ -43,7 +43,7 @@ #include #include -#include "lib/ramtest.c" +#include #include Index: src/mainboard/supermicro/h8qme_fam10/romstage.c =================================================================== --- src/mainboard/supermicro/h8qme_fam10/romstage.c (revision 5908) +++ src/mainboard/supermicro/h8qme_fam10/romstage.c (working copy) @@ -43,7 +43,7 @@ #include #include -#include "lib/ramtest.c" +#include #include Index: src/mainboard/kontron/986lcd-m/romstage.c =================================================================== --- src/mainboard/kontron/986lcd-m/romstage.c (revision 5908) +++ src/mainboard/kontron/986lcd-m/romstage.c (working copy) @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -35,21 +36,17 @@ #include #include -#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "superio/winbond/w83627thg/w83627thg_early_serial.c" -#include "northbridge/intel/i945/udelay.c" +void enable_smbus(void); #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) + +void setup_ich7_gpios(void) { printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ @@ -65,18 +62,6 @@ outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ Index: src/mainboard/traverse/geos/romstage.c =================================================================== --- src/mainboard/traverse/geos/romstage.c (revision 5908) +++ src/mainboard/traverse/geos/romstage.c (working copy) @@ -25,7 +25,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/digitallogic/msm800sev/romstage.c =================================================================== --- src/mainboard/digitallogic/msm800sev/romstage.c (revision 5908) +++ src/mainboard/digitallogic/msm800sev/romstage.c (working copy) @@ -6,7 +6,6 @@ #include #include #include -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/digitallogic/adl855pc/romstage.c =================================================================== --- src/mainboard/digitallogic/adl855pc/romstage.c (revision 5908) +++ src/mainboard/digitallogic/adl855pc/romstage.c (working copy) @@ -8,7 +8,6 @@ #include "pc80/udelay_io.c" #include #include -#include "lib/ramtest.c" #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h" Index: src/mainboard/gigabyte/m57sli/romstage.c =================================================================== --- src/mainboard/gigabyte/m57sli/romstage.c (revision 5908) +++ src/mainboard/gigabyte/m57sli/romstage.c (working copy) @@ -53,7 +53,6 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" #include Index: src/mainboard/gigabyte/ma78gm/romstage.c =================================================================== --- src/mainboard/gigabyte/ma78gm/romstage.c (revision 5908) +++ src/mainboard/gigabyte/ma78gm/romstage.c (working copy) @@ -45,10 +45,10 @@ #include #include #include -#include "lib/ramtest.c" #include #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Index: src/mainboard/gigabyte/ga_2761gxdk/romstage.c =================================================================== --- src/mainboard/gigabyte/ga_2761gxdk/romstage.c (revision 5908) +++ src/mainboard/gigabyte/ga_2761gxdk/romstage.c (working copy) @@ -55,7 +55,6 @@ #include "southbridge/sis/sis966/sis966_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" #include Index: src/mainboard/gigabyte/ma785gmt/romstage.c =================================================================== --- src/mainboard/gigabyte/ma785gmt/romstage.c (revision 5908) +++ src/mainboard/gigabyte/ma785gmt/romstage.c (working copy) @@ -41,10 +41,10 @@ #include #include #include -#include "lib/ramtest.c" #include #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Index: src/mainboard/amd/rumba/romstage.c =================================================================== --- src/mainboard/amd/rumba/romstage.c (revision 5908) +++ src/mainboard/amd/rumba/romstage.c (working copy) @@ -4,7 +4,6 @@ #include #include #include -#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Index: src/mainboard/amd/mahogany_fam10/romstage.c =================================================================== --- src/mainboard/amd/mahogany_fam10/romstage.c (revision 5908) +++ src/mainboard/amd/mahogany_fam10/romstage.c (working copy) @@ -45,10 +45,10 @@ #include #include #include -#include "lib/ramtest.c" #include #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Index: src/mainboard/amd/tilapia_fam10/romstage.c =================================================================== --- src/mainboard/amd/tilapia_fam10/romstage.c (revision 5908) +++ src/mainboard/amd/tilapia_fam10/romstage.c (working copy) @@ -45,10 +45,10 @@ #include #include #include -#include "lib/ramtest.c" #include #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Index: src/mainboard/amd/norwich/romstage.c =================================================================== --- src/mainboard/amd/norwich/romstage.c (revision 5908) +++ src/mainboard/amd/norwich/romstage.c (working copy) @@ -25,7 +25,6 @@ #include #include #include -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/amd/serengeti_cheetah_fam10/romstage.c =================================================================== --- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c (revision 5908) +++ src/mainboard/amd/serengeti_cheetah_fam10/romstage.c (working copy) @@ -45,11 +45,11 @@ #include #include #include -#include "lib/ramtest.c" #include #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Index: src/mainboard/amd/db800/romstage.c =================================================================== --- src/mainboard/amd/db800/romstage.c (revision 5908) +++ src/mainboard/amd/db800/romstage.c (working copy) @@ -25,7 +25,6 @@ #include #include #include -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/rca/rm4100/romstage.c =================================================================== --- src/mainboard/rca/rm4100/romstage.c (revision 5908) +++ src/mainboard/rca/rm4100/romstage.c (working copy) @@ -27,7 +27,7 @@ #include #include "pc80/udelay_io.c" #include -#include "lib/ramtest.c" +#include #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" Index: src/mainboard/iei/pcisa-lx-800-r10/romstage.c =================================================================== --- src/mainboard/iei/pcisa-lx-800-r10/romstage.c (revision 5908) +++ src/mainboard/iei/pcisa-lx-800-r10/romstage.c (working copy) @@ -25,7 +25,6 @@ #include #include #include -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/iei/kino-780am2-fam10/romstage.c =================================================================== --- src/mainboard/iei/kino-780am2-fam10/romstage.c (revision 5908) +++ src/mainboard/iei/kino-780am2-fam10/romstage.c (working copy) @@ -48,10 +48,10 @@ #include #include #include -#include "lib/ramtest.c" #include #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Index: src/mainboard/hp/dl145_g1/romstage.c =================================================================== --- src/mainboard/hp/dl145_g1/romstage.c (revision 5908) +++ src/mainboard/hp/dl145_g1/romstage.c (working copy) @@ -13,7 +13,6 @@ #include #include #include -#include "lib/ramtest.c" #include Index: src/mainboard/hp/dl145_g3/romstage.c =================================================================== --- src/mainboard/hp/dl145_g3/romstage.c (revision 5908) +++ src/mainboard/hp/dl145_g3/romstage.c (working copy) @@ -55,7 +55,6 @@ #include #include -#include "lib/ramtest.c" #include Index: src/mainboard/hp/dl165_g6_fam10/romstage.c =================================================================== --- src/mainboard/hp/dl165_g6_fam10/romstage.c (revision 5908) +++ src/mainboard/hp/dl165_g6_fam10/romstage.c (working copy) @@ -49,11 +49,11 @@ #include #include "option_table.h" #include -#include "lib/ramtest.c" #include #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include #include "cpu/amd/model_10xxx/apic_timer.c" #include "lib/delay.c" Index: src/mainboard/tyan/s2912/romstage.c =================================================================== --- src/mainboard/tyan/s2912/romstage.c (revision 5908) +++ src/mainboard/tyan/s2912/romstage.c (working copy) @@ -53,7 +53,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" +#include #include Index: src/mainboard/tyan/s2850/romstage.c =================================================================== --- src/mainboard/tyan/s2850/romstage.c (revision 5908) +++ src/mainboard/tyan/s2850/romstage.c (working copy) @@ -9,7 +9,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include #include "northbridge/amd/amdk8/incoherent_ht.c" Index: src/mainboard/tyan/s2735/romstage.c =================================================================== --- src/mainboard/tyan/s2735/romstage.c (revision 5908) +++ src/mainboard/tyan/s2735/romstage.c (working copy) @@ -8,7 +8,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" Index: src/mainboard/tyan/s2880/romstage.c =================================================================== --- src/mainboard/tyan/s2880/romstage.c (revision 5908) +++ src/mainboard/tyan/s2880/romstage.c (working copy) @@ -9,7 +9,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include #include "northbridge/amd/amdk8/incoherent_ht.c" Index: src/mainboard/tyan/s2881/romstage.c =================================================================== --- src/mainboard/tyan/s2881/romstage.c (revision 5908) +++ src/mainboard/tyan/s2881/romstage.c (working copy) @@ -13,7 +13,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include Index: src/mainboard/tyan/s2882/romstage.c =================================================================== --- src/mainboard/tyan/s2882/romstage.c (revision 5908) +++ src/mainboard/tyan/s2882/romstage.c (working copy) @@ -9,7 +9,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include #include "northbridge/amd/amdk8/incoherent_ht.c" Index: src/mainboard/tyan/s2891/romstage.c =================================================================== --- src/mainboard/tyan/s2891/romstage.c (revision 5908) +++ src/mainboard/tyan/s2891/romstage.c (working copy) @@ -14,7 +14,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include Index: src/mainboard/tyan/s4880/romstage.c =================================================================== --- src/mainboard/tyan/s4880/romstage.c (revision 5908) +++ src/mainboard/tyan/s4880/romstage.c (working copy) @@ -9,7 +9,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include #include "northbridge/amd/amdk8/incoherent_ht.c" Index: src/mainboard/tyan/s2892/romstage.c =================================================================== --- src/mainboard/tyan/s2892/romstage.c (revision 5908) +++ src/mainboard/tyan/s2892/romstage.c (working copy) @@ -14,7 +14,7 @@ #include #include -#include "lib/ramtest.c" +#include #include Index: src/mainboard/tyan/s2875/romstage.c =================================================================== --- src/mainboard/tyan/s2875/romstage.c (revision 5908) +++ src/mainboard/tyan/s2875/romstage.c (working copy) @@ -9,7 +9,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include #include "northbridge/amd/amdk8/incoherent_ht.c" Index: src/mainboard/tyan/s4882/romstage.c =================================================================== --- src/mainboard/tyan/s4882/romstage.c (revision 5908) +++ src/mainboard/tyan/s4882/romstage.c (working copy) @@ -8,7 +8,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include #include "northbridge/amd/amdk8/incoherent_ht.c" Index: src/mainboard/tyan/s2885/romstage.c =================================================================== --- src/mainboard/tyan/s2885/romstage.c (revision 5908) +++ src/mainboard/tyan/s2885/romstage.c (working copy) @@ -8,7 +8,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include Index: src/mainboard/tyan/s2895/romstage.c =================================================================== --- src/mainboard/tyan/s2895/romstage.c (revision 5908) +++ src/mainboard/tyan/s2895/romstage.c (working copy) @@ -15,7 +15,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" Index: src/mainboard/tyan/s2912_fam10/romstage.c =================================================================== --- src/mainboard/tyan/s2912_fam10/romstage.c (revision 5908) +++ src/mainboard/tyan/s2912_fam10/romstage.c (working copy) @@ -46,7 +46,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" +#include #include Index: src/mainboard/pcengines/alix1c/romstage.c =================================================================== --- src/mainboard/pcengines/alix1c/romstage.c (revision 5908) +++ src/mainboard/pcengines/alix1c/romstage.c (working copy) @@ -26,7 +26,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/pcengines/alix2d/romstage.c =================================================================== --- src/mainboard/pcengines/alix2d/romstage.c (revision 5908) +++ src/mainboard/pcengines/alix2d/romstage.c (working copy) @@ -26,7 +26,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/artecgroup/dbe61/romstage.c =================================================================== --- src/mainboard/artecgroup/dbe61/romstage.c (revision 5908) +++ src/mainboard/artecgroup/dbe61/romstage.c (working copy) @@ -26,7 +26,6 @@ #include #include #include -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/lippert/roadrunner-lx/romstage.c =================================================================== --- src/mainboard/lippert/roadrunner-lx/romstage.c (revision 5908) +++ src/mainboard/lippert/roadrunner-lx/romstage.c (working copy) @@ -28,7 +28,6 @@ #include #include #include -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/lippert/hurricane-lx/romstage.c =================================================================== --- src/mainboard/lippert/hurricane-lx/romstage.c (revision 5908) +++ src/mainboard/lippert/hurricane-lx/romstage.c (working copy) @@ -28,7 +28,6 @@ #include #include #include -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/lippert/frontrunner/romstage.c =================================================================== --- src/mainboard/lippert/frontrunner/romstage.c (revision 5908) +++ src/mainboard/lippert/frontrunner/romstage.c (working copy) @@ -4,7 +4,6 @@ #include #include #include -#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Index: src/mainboard/lippert/spacerunner-lx/romstage.c =================================================================== --- src/mainboard/lippert/spacerunner-lx/romstage.c (revision 5908) +++ src/mainboard/lippert/spacerunner-lx/romstage.c (working copy) @@ -29,7 +29,6 @@ #include #include #include -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/lippert/literunner-lx/romstage.c =================================================================== --- src/mainboard/lippert/literunner-lx/romstage.c (revision 5908) +++ src/mainboard/lippert/literunner-lx/romstage.c (working copy) @@ -29,7 +29,6 @@ #include #include #include -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/via/epia-m700/romstage.c =================================================================== --- src/mainboard/via/epia-m700/romstage.c (revision 5908) +++ src/mainboard/via/epia-m700/romstage.c (working copy) @@ -33,7 +33,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include "northbridge/via/vx800/vx800.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" Index: src/mainboard/via/vt8454c/romstage.c =================================================================== --- src/mainboard/via/vt8454c/romstage.c (revision 5908) +++ src/mainboard/via/vt8454c/romstage.c (working copy) @@ -27,7 +27,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include "northbridge/via/cx700/raminit.h" #include "cpu/x86/bist.h" Index: src/mainboard/via/epia-cn/romstage.c =================================================================== --- src/mainboard/via/epia-cn/romstage.c (revision 5908) +++ src/mainboard/via/epia-cn/romstage.c (working copy) @@ -27,7 +27,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" Index: src/mainboard/via/pc2500e/romstage.c =================================================================== --- src/mainboard/via/pc2500e/romstage.c (revision 5908) +++ src/mainboard/via/pc2500e/romstage.c (working copy) @@ -27,7 +27,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" Index: src/mainboard/lanner/em8510/romstage.c =================================================================== --- src/mainboard/lanner/em8510/romstage.c (revision 5908) +++ src/mainboard/lanner/em8510/romstage.c (working copy) @@ -30,7 +30,6 @@ #include "pc80/udelay_io.c" #include #include -#include "lib/ramtest.c" #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h" Index: src/mainboard/ibase/mb899/romstage.c =================================================================== --- src/mainboard/ibase/mb899/romstage.c (revision 5908) +++ src/mainboard/ibase/mb899/romstage.c (working copy) @@ -26,6 +26,7 @@ #include #include #include +#include #include "superio/winbond/w83627ehg/w83627ehg.h" @@ -34,21 +35,17 @@ #include #include -#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" -#include "northbridge/intel/i945/udelay.c" - #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) + +void enable_smbus(void); + +void setup_ich7_gpios(void) { printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ @@ -64,18 +61,6 @@ outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ Index: src/mainboard/roda/rk886ex/romstage.c =================================================================== --- src/mainboard/roda/rk886ex/romstage.c (revision 5908) +++ src/mainboard/roda/rk886ex/romstage.c (working copy) @@ -28,24 +28,20 @@ #include #include #include +#include #include #include #include -#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "southbridge/intel/i82801gx/i82801gx.h" -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" +void enable_smbus(void); -#include "northbridge/intel/i945/udelay.c" - -#include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) +void setup_ich7_gpios(void) { printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ @@ -61,18 +57,6 @@ outl(0x00010030, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ Index: src/mainboard/msi/ms7135/romstage.c =================================================================== --- src/mainboard/msi/ms7135/romstage.c (revision 5908) +++ src/mainboard/msi/ms7135/romstage.c (working copy) @@ -49,7 +49,6 @@ #include #include -#include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" Index: src/mainboard/msi/ms9652_fam10/romstage.c =================================================================== --- src/mainboard/msi/ms9652_fam10/romstage.c (revision 5908) +++ src/mainboard/msi/ms9652_fam10/romstage.c (working copy) @@ -46,7 +46,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" +#include #include Index: src/mainboard/msi/ms7260/romstage.c =================================================================== --- src/mainboard/msi/ms7260/romstage.c (revision 5908) +++ src/mainboard/msi/ms7260/romstage.c (working copy) @@ -56,12 +56,12 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" #include #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" +#include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" Index: src/mainboard/arima/hdama/romstage.c =================================================================== --- src/mainboard/arima/hdama/romstage.c (revision 5908) +++ src/mainboard/arima/hdama/romstage.c (working copy) @@ -7,7 +7,6 @@ #include #include #include -#include "lib/ramtest.c" #include #include "northbridge/amd/amdk8/incoherent_ht.c" Index: src/mainboard/sunw/ultra40/romstage.c =================================================================== --- src/mainboard/sunw/ultra40/romstage.c (revision 5908) +++ src/mainboard/sunw/ultra40/romstage.c (working copy) @@ -16,7 +16,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include #include "northbridge/amd/amdk8/incoherent_ht.c" Index: src/mainboard/newisys/khepri/romstage.c =================================================================== --- src/mainboard/newisys/khepri/romstage.c (revision 5908) +++ src/mainboard/newisys/khepri/romstage.c (working copy) @@ -14,7 +14,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include Index: src/mainboard/jetway/pa78vm5/romstage.c =================================================================== --- src/mainboard/jetway/pa78vm5/romstage.c (revision 5908) +++ src/mainboard/jetway/pa78vm5/romstage.c (working copy) @@ -46,10 +46,10 @@ #include #include #include -#include "lib/ramtest.c" #include #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Index: src/mainboard/jetway/j7f24/romstage.c =================================================================== --- src/mainboard/jetway/j7f24/romstage.c (revision 5908) +++ src/mainboard/jetway/j7f24/romstage.c (working copy) @@ -27,13 +27,13 @@ #include #include #include -#include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/fintek/f71805f/f71805f_early_serial.c" +#include #if CONFIG_TTYS0_BASE == 0x2f8 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2) Index: src/mainboard/winent/pl6064/romstage.c =================================================================== --- src/mainboard/winent/pl6064/romstage.c (revision 5908) +++ src/mainboard/winent/pl6064/romstage.c (working copy) @@ -26,7 +26,7 @@ #include #include #include -#include "lib/ramtest.c" +#include #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include Index: src/mainboard/ibm/e326/romstage.c =================================================================== --- src/mainboard/ibm/e326/romstage.c (revision 5908) +++ src/mainboard/ibm/e326/romstage.c (working copy) @@ -9,7 +9,6 @@ #include #include #include -#include "lib/ramtest.c" #include #include "northbridge/amd/amdk8/incoherent_ht.c" Index: src/mainboard/ibm/e325/romstage.c =================================================================== --- src/mainboard/ibm/e325/romstage.c (revision 5908) +++ src/mainboard/ibm/e325/romstage.c (working copy) @@ -9,7 +9,6 @@ #include #include #include -#include "lib/ramtest.c" #include #include "northbridge/amd/amdk8/incoherent_ht.c" Index: src/mainboard/nvidia/l1_2pvv/romstage.c =================================================================== --- src/mainboard/nvidia/l1_2pvv/romstage.c (revision 5908) +++ src/mainboard/nvidia/l1_2pvv/romstage.c (working copy) @@ -53,7 +53,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" +#include #include Index: src/mainboard/intel/d945gclf/romstage.c =================================================================== --- src/mainboard/intel/d945gclf/romstage.c (revision 5908) +++ src/mainboard/intel/d945gclf/romstage.c (working copy) @@ -26,6 +26,7 @@ #include #include #include +#include #include "superio/smsc/lpc47m15x/lpc47m15x.h" @@ -34,21 +35,17 @@ #include #include -#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c" -#include "northbridge/intel/i945/udelay.c" - #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) + +void enable_smbus(void); + +void setup_ich7_gpios(void) { /* TODO: This is highly board specific and should be moved */ printk(BIOS_DEBUG, " GPIOS..."); @@ -65,18 +62,6 @@ outl(0x000300fd, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ Index: src/mainboard/intel/mtarvon/romstage.c =================================================================== --- src/mainboard/intel/mtarvon/romstage.c (revision 5908) +++ src/mainboard/intel/mtarvon/romstage.c (working copy) @@ -28,7 +28,6 @@ #include #include #include -#include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" #include "northbridge/intel/i3100/raminit.h" Index: src/mainboard/intel/d810e2cb/romstage.c =================================================================== --- src/mainboard/intel/d810e2cb/romstage.c (revision 5908) +++ src/mainboard/intel/d810e2cb/romstage.c (working copy) @@ -26,7 +26,6 @@ #include #include #include -#include "lib/ramtest.c" #include "southbridge/intel/i82801bx/i82801bx.h" #include "southbridge/intel/i82801bx/i82801bx_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" @@ -36,6 +35,7 @@ #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "gpio.c" +#include #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) Index: src/mainboard/intel/eagleheights/romstage.c =================================================================== --- src/mainboard/intel/eagleheights/romstage.c (revision 5908) +++ src/mainboard/intel/eagleheights/romstage.c (working copy) @@ -34,7 +34,6 @@ #include #include -#include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" #include "reset.c" Index: src/mainboard/asus/m4a785-m/romstage.c =================================================================== --- src/mainboard/asus/m4a785-m/romstage.c (revision 5908) +++ src/mainboard/asus/m4a785-m/romstage.c (working copy) @@ -45,10 +45,10 @@ #include #include #include -#include "lib/ramtest.c" #include #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Index: src/mainboard/asus/a8n_e/romstage.c =================================================================== --- src/mainboard/asus/a8n_e/romstage.c (revision 5908) +++ src/mainboard/asus/a8n_e/romstage.c (working copy) @@ -48,7 +48,6 @@ #include #include -#include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" Index: src/lib/Makefile.inc =================================================================== --- src/lib/Makefile.inc (revision 5908) +++ src/lib/Makefile.inc (working copy) @@ -21,6 +21,7 @@ romstage-y += memcmp.c romstage-y += cbfs.c romstage-y += lzma.c +romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c #romstage-y += lzmadecode.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c Index: src/lib/ramtest.c =================================================================== --- src/lib/ramtest.c (revision 5908) +++ src/lib/ramtest.c (working copy) @@ -1,4 +1,6 @@ +#include #include /* Prototypes */ +#include static void write_phys(unsigned long addr, u32 value) { Index: src/northbridge/intel/i945/i945.h =================================================================== --- src/northbridge/intel/i945/i945.h (revision 5908) +++ src/northbridge/intel/i945/i945.h (working copy) @@ -333,5 +333,22 @@ static inline void barrier(void) { asm("" ::: "memory"); } +int i945_silicon_revision(void); +void i945_early_initialization(void); +void i945_late_initialization(void); + +/* provided by southbridge code */ +int smbus_read_byte(unsigned device, unsigned address); + +/* provided by mainboard code */ +void setup_ich7_gpios(void); + +/* debugging functions */ +void print_pci_devices(void); +void dump_pci_device(unsigned dev); +void dump_pci_devices(void); +void dump_spd_registers(void); +void dump_mem(unsigned start, unsigned end); + #endif #endif Index: src/northbridge/intel/i945/early_init.c =================================================================== --- src/northbridge/intel/i945/early_init.c (revision 5908) +++ src/northbridge/intel/i945/early_init.c (working copy) @@ -17,10 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include +#include +#include +#include +#include +#include #include "i945.h" #include "pcie_config.c" -static int i945_silicon_revision(void) +int i945_silicon_revision(void) { return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION); } @@ -856,7 +862,7 @@ pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); } -static void i945_early_initialization(void) +void i945_early_initialization(void) { /* Print some chipset specific information */ switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) { @@ -879,7 +885,7 @@ RCBA32(0x2010) |= (1 << 10); } -static void i945_late_initialization(void) +void i945_late_initialization(void) { i945_setup_egress_port(); Index: src/northbridge/intel/i945/raminit.c =================================================================== --- src/northbridge/intel/i945/raminit.c (revision 5908) +++ src/northbridge/intel/i945/raminit.c (working copy) @@ -17,10 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include #include +#include +#include #include "raminit.h" #include "i945.h" @@ -45,6 +48,11 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + static __attribute__((noinline)) void do_ram_command(u32 command) { u32 reg32; Index: src/northbridge/intel/i945/Makefile.inc =================================================================== --- src/northbridge/intel/i945/Makefile.inc (revision 5908) +++ src/northbridge/intel/i945/Makefile.inc (working copy) @@ -20,3 +20,9 @@ driver-y += northbridge.c driver-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c + +romstage-y += udelay.c +romstage-y += raminit.c +romstage-y += early_init.c +romstage-y += errata.c +romstage-y += debug.c Index: src/northbridge/intel/i945/raminit.h =================================================================== --- src/northbridge/intel/i945/raminit.h (revision 5908) +++ src/northbridge/intel/i945/raminit.h (working copy) @@ -71,4 +71,6 @@ void sdram_initialize(int boot_path); unsigned long get_top_of_ram(void); int fixup_i945_errata(void); +void udelay(u32 us); + #endif /* RAMINIT_H */ Index: src/northbridge/intel/i945/errata.c =================================================================== --- src/northbridge/intel/i945/errata.c (revision 5908) +++ src/northbridge/intel/i945/errata.c (working copy) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include +#include "i945.h" #include "raminit.h" int fixup_i945_errata(void) Index: src/northbridge/intel/i945/udelay.c =================================================================== --- src/northbridge/intel/i945/udelay.c (revision 5908) +++ src/northbridge/intel/i945/udelay.c (working copy) @@ -18,6 +18,7 @@ */ #include +#include #include #include Index: src/northbridge/intel/i945/debug.c =================================================================== --- src/northbridge/intel/i945/debug.c (revision 5908) +++ src/northbridge/intel/i945/debug.c (working copy) @@ -19,11 +19,18 @@ * MA 02110-1301 USA */ +#include +#include +#include +#include +#include +#include "i945.h" + #define SMBUS_MEM_DEVICE_START 0x50 #define SMBUS_MEM_DEVICE_END 0x53 #define SMBUS_MEM_DEVICE_INC 1 -static inline void print_pci_devices(void) +void print_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -42,7 +49,7 @@ } } -static inline void dump_pci_device(unsigned dev) +void dump_pci_device(unsigned dev) { int i; @@ -61,7 +68,7 @@ } } -static inline void dump_pci_devices(void) +void dump_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -78,7 +85,7 @@ } } -static inline void dump_spd_registers(void) +void dump_spd_registers(void) { unsigned device; device = SMBUS_MEM_DEVICE_START; @@ -103,7 +110,7 @@ } } -static inline void dump_mem(unsigned start, unsigned end) +void dump_mem(unsigned start, unsigned end) { unsigned i; print_debug("dump_mem:"); Index: src/pc80/Makefile.inc =================================================================== --- src/pc80/Makefile.inc (revision 5908) +++ src/pc80/Makefile.inc (working copy) @@ -6,6 +6,7 @@ romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c romstage-$(CONFIG_CACHE_AS_RAM) += serial.c +romstage-$(CONFIG_USBDEBUG) += usbdebug_serial.c subdirs-y += vga $(obj)/pc80/mc146818rtc.ramstage.o : $(OPTION_TABLE_H)