Patchwork De-define CK804 flags

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Submitter Myles Watson
Date 2010-10-05 15:32:50
Message ID <AANLkTim4QOrQXGT5OJZbVz878n1O5qvdONtyDTuJ3vxP@mail.gmail.com>
Download mbox | patch
Permalink /patch/2044/
State Accepted
Headers show

Comments

Myles Watson - 2010-10-05 15:32:50
On Tue, Oct 5, 2010 at 8:41 AM, Patrick Georgi <patrick@georgi-clan.de> wrote:
> Hi,
>
> attached patch moves a couple more config flags out of romstage:
> CK804_USE_NIC, CK804_USE_ACI.
>
> Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>

I'd like to keep CK804 & MCP55 as similar as possible.  Patches attached.

Signed-off-by: Myles Watson <mylesgw@gmail.com>

Thanks,
Myles
Peter Stuge - 2010-10-05 16:04:59
Myles Watson wrote:
> > attached patch moves a couple more config flags out of romstage:
> > CK804_USE_NIC, CK804_USE_ACI.
> >
> > Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
> Acked-by: Myles Watson <mylesgw@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>


> I'd like to keep CK804 & MCP55 as similar as possible.  Patches attached.
> 
> Signed-off-by: Myles Watson <mylesgw@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>
Patrick Georgi - 2010-10-05 17:16:38
Am 05.10.2010 17:32, schrieb Myles Watson:
> On Tue, Oct 5, 2010 at 8:41 AM, Patrick Georgi <patrick@georgi-clan.de> wrote:
>> Hi,
>>
>> attached patch moves a couple more config flags out of romstage:
>> CK804_USE_NIC, CK804_USE_ACI.
>>
>> Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
> Acked-by: Myles Watson <mylesgw@gmail.com>
> 
> I'd like to keep CK804 & MCP55 as similar as possible.  Patches attached.
One issue: you didn't handle all MCP55_NUMs, there are some #defines
left. I didn't work on the _NUM stuff at all as I don't know its meaning.


Patrick
Myles Watson - 2010-10-05 18:01:51
On Tue, Oct 5, 2010 at 11:16 AM, Patrick Georgi <patrick@georgi-clan.de> wrote:
> Am 05.10.2010 17:32, schrieb Myles Watson:
>> On Tue, Oct 5, 2010 at 8:41 AM, Patrick Georgi <patrick@georgi-clan.de> wrote:
>>> Hi,
>>>
>>> attached patch moves a couple more config flags out of romstage:
>>> CK804_USE_NIC, CK804_USE_ACI.
>>>
>>> Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
>> Acked-by: Myles Watson <mylesgw@gmail.com>
>>
>> I'd like to keep CK804 & MCP55 as similar as possible.  Patches attached.
> Acked-by: Peter Stuge <peter@stuge.se>
Rev 5912.

> One issue: you didn't handle all MCP55_NUMs, there are some #defines
> left.
I didn't see any, but I'll fix them if you point them out.

> I didn't work on the _NUM stuff at all as I don't know its meaning.
It is how many chips there are on the board.  Most boards only have
one CK804 or MCP55, but some have two.

Thanks,
Myles

Patch

Index: svn/src/southbridge/nvidia/ck804/Kconfig
===================================================================
--- svn.orig/src/southbridge/nvidia/ck804/Kconfig
+++ svn/src/southbridge/nvidia/ck804/Kconfig
@@ -24,3 +24,6 @@  config CK804_USE_ACI
 	bool
 	default n if SOUTHBRIDGE_NVIDIA_CK804
 
+config CK804_NUM
+	int
+	default 1 if SOUTHBRIDGE_NVIDIA_CK804
Index: svn/src/southbridge/nvidia/mcp55/Kconfig
===================================================================
--- svn.orig/src/southbridge/nvidia/mcp55/Kconfig
+++ svn/src/southbridge/nvidia/mcp55/Kconfig
@@ -23,3 +23,6 @@  config MCP55_USE_AZA
 	bool
 	default n if SOUTHBRIDGE_NVIDIA_MCP55
 
+config MCP55_NUM
+	int
+	default 1 if SOUTHBRIDGE_NVIDIA_MCP55
Index: svn/src/mainboard/asus/a8n_e/romstage.c
===================================================================
--- svn.orig/src/mainboard/asus/a8n_e/romstage.c
+++ svn/src/mainboard/asus/a8n_e/romstage.c
@@ -42,10 +42,6 @@ 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-
-/* Used by ck894_early_setup(). */
-#define CK804_NUM 1
-
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
Index: svn/src/mainboard/gigabyte/m57sli/romstage.c
===================================================================
--- svn.orig/src/mainboard/gigabyte/m57sli/romstage.c
+++ svn/src/mainboard/gigabyte/m57sli/romstage.c
@@ -90,8 +90,6 @@  static inline int spd_read_byte(unsigned
 	return smbus_read_byte(device, address);
 }
 
-#define MCP55_NUM 1
-
 #define MCP55_PCI_E_X_0 0
 
 #define MCP55_MB_SETUP \
Index: svn/src/mainboard/msi/ms7260/romstage.c
===================================================================
--- svn.orig/src/mainboard/msi/ms7260/romstage.c
+++ svn/src/mainboard/msi/ms7260/romstage.c
@@ -92,7 +92,6 @@  static inline int spd_read_byte(unsigned
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 1
 #define MCP55_PCI_E_X_0 0
 
 #define MCP55_MB_SETUP \
Index: svn/src/mainboard/msi/ms9282/romstage.c
===================================================================
--- svn.orig/src/mainboard/msi/ms9282/romstage.c
+++ svn/src/mainboard/msi/ms9282/romstage.c
@@ -105,7 +105,6 @@  static inline int spd_read_byte(unsigned
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 1
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 //set GPIO to input mode
 #define MCP55_MB_SETUP \
Index: svn/src/mainboard/msi/ms9652_fam10/romstage.c
===================================================================
--- svn.orig/src/mainboard/msi/ms9652_fam10/romstage.c
+++ svn/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -89,8 +89,6 @@  static inline int spd_read_byte(unsigned
 
 #include "cpu/amd/quadcore/quadcore.c"
 
-#define MCP55_NUM 1
-
 #define MCP55_PCI_E_X_0 1
 
 #define MCP55_MB_SETUP \
Index: svn/src/mainboard/nvidia/l1_2pvv/Kconfig
===================================================================
--- svn.orig/src/mainboard/nvidia/l1_2pvv/Kconfig
+++ svn/src/mainboard/nvidia/l1_2pvv/Kconfig
@@ -46,6 +46,10 @@  config MEM_TRAIN_SEQ
 	int
 	default 1
 
+config MCP55_NUM
+	int
+	default 2
+
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 2
Index: svn/src/mainboard/nvidia/l1_2pvv/romstage.c
===================================================================
--- svn.orig/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ svn/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -100,8 +100,6 @@  static inline int spd_read_byte(unsigned
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 2
-
 #define MCP55_PCI_E_X_0 2
 #define MCP55_PCI_E_X_1 4
 
Index: svn/src/mainboard/supermicro/h8dme/romstage.c
===================================================================
--- svn.orig/src/mainboard/supermicro/h8dme/romstage.c
+++ svn/src/mainboard/supermicro/h8dme/romstage.c
@@ -155,8 +155,6 @@  static inline int spd_read_byte(unsigned
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 1
-
 #define MCP55_PCI_E_X_0 4
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
Index: svn/src/mainboard/supermicro/h8dmr/romstage.c
===================================================================
--- svn.orig/src/mainboard/supermicro/h8dmr/romstage.c
+++ svn/src/mainboard/supermicro/h8dmr/romstage.c
@@ -100,8 +100,6 @@  static inline int spd_read_byte(unsigned
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 1
-
 #define MCP55_PCI_E_X_0 4
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
Index: svn/src/mainboard/supermicro/h8dmr_fam10/romstage.c
===================================================================
--- svn.orig/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ svn/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -89,8 +89,6 @@  static inline int spd_read_byte(unsigned
 
 #include "cpu/amd/quadcore/quadcore.c"
 
-#define MCP55_NUM 1
-
 #define MCP55_PCI_E_X_0 4
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
Index: svn/src/mainboard/supermicro/h8qme_fam10/romstage.c
===================================================================
--- svn.orig/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ svn/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -92,8 +92,6 @@  static inline int spd_read_byte(unsigned
 
 #include "cpu/amd/quadcore/quadcore.c"
 
-#define MCP55_NUM 1
-
 #define MCP55_PCI_E_X_0 4
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
Index: svn/src/mainboard/tyan/s2891/romstage.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2891/romstage.c
+++ svn/src/mainboard/tyan/s2891/romstage.c
@@ -62,12 +62,9 @@  static inline int spd_read_byte(unsigned
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define CK804_NUM 1
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
 
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
Index: svn/src/mainboard/tyan/s2912/romstage.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2912/romstage.c
+++ svn/src/mainboard/tyan/s2912/romstage.c
@@ -100,8 +100,6 @@  static inline int spd_read_byte(unsigned
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_NUM 1
-
 #define MCP55_PCI_E_X_0 1
 
 #define MCP55_MB_SETUP \
Index: svn/src/mainboard/tyan/s2912_fam10/romstage.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2912_fam10/romstage.c
+++ svn/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -89,8 +89,6 @@  static inline int spd_read_byte(unsigned
 
 #include "cpu/amd/quadcore/quadcore.c"
 
-#define MCP55_NUM 1
-
 #define MCP55_PCI_E_X_0 1
 
 #define MCP55_MB_SETUP \
Index: svn/src/southbridge/nvidia/ck804/ck804_early_setup.c
===================================================================
--- svn.orig/src/southbridge/nvidia/ck804/ck804_early_setup.c
+++ svn/src/southbridge/nvidia/ck804/ck804_early_setup.c
@@ -52,7 +52,7 @@  static void setup_ss_table(unsigned inde
 #define CK804_PCI_E_X 4
 #endif
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 #define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000)
 #define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000)
 #ifndef CK804B_BUSN
@@ -81,12 +81,12 @@  static void ck804_early_set_port(void)
 {
 	static const unsigned int ctrl_devport_conf[] = {
 		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 		PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE,
 #endif
 
 		PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 		PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE,
 #endif
 	};
@@ -98,11 +98,11 @@  static void ck804_early_clear_port(void)
 {
 	static const unsigned int ctrl_devport_conf_clear[] = {
 		PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 		PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
 #endif
 		PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 		PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
 #endif
 	};
@@ -118,7 +118,7 @@  static void ck804_early_setup(void)
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000,
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00,
@@ -133,7 +133,7 @@  static void ck804_early_setup(void)
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000,
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f,
@@ -147,7 +147,7 @@  static void ck804_early_setup(void)
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010,
 #endif
@@ -156,7 +156,7 @@  static void ck804_early_setup(void)
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000,
@@ -165,7 +165,7 @@  static void ck804_early_setup(void)
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100,
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff,
@@ -182,7 +182,7 @@  static void ck804_early_setup(void)
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32),
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16),
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
@@ -192,7 +192,7 @@  static void ck804_early_setup(void)
 #endif
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
 #endif
 
@@ -218,7 +218,7 @@  static void ck804_early_setup(void)
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
 	RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,
-#if  CK804_NUM > 1
+#if  CONFIG_CK804_NUM > 1
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,
@@ -232,19 +232,19 @@  static void ck804_early_setup(void)
 #endif
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10),
 #endif
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
 #endif
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
 #endif
 
@@ -263,11 +263,11 @@  static void ck804_early_setup(void)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
 #endif
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2),
 #endif
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 #if CONFIG_CK804_USE_NIC
 	RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040,
 	RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
@@ -288,7 +288,7 @@  static void ck804_early_setup(void)
 	setup_ss_table(ANACTRL_IO_BASE + 0xb0, ANACTRL_IO_BASE + 0xb4, ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64);
 	setup_ss_table(ANACTRL_IO_BASE + 0xc0, ANACTRL_IO_BASE + 0xc4, ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);
 
-#if CK804_NUM > 1
+#if CONFIG_CK804_NUM > 1
 	setup_ss_table(CK804B_ANACTRL_IO_BASE + 0x40, CK804B_ANACTRL_IO_BASE + 0x44, CK804B_ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64);
 	setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xb0, CK804B_ANACTRL_IO_BASE + 0xb4, CK804B_ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64);
 	setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);
Index: svn/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
===================================================================
--- svn.orig/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
+++ svn/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
@@ -391,7 +391,7 @@  static int mcp55_early_setup_x(void)
 				devn[mcp55_num] = devnx;
 				io_base[mcp55_num] = ht_c_index * HT_CHAIN_IOBASE_D; // we may have ht chain other than MCP55
 				mcp55_num++;
-				if(mcp55_num == MCP55_NUM) goto out;
+				if(mcp55_num == CONFIG_MCP55_NUM) goto out;
 				break; // only one MCP55 on one chain
 			}
 		}