Patchwork Convert Intel 82371AB/EB/MB boards to TINY_BOOTBLOCK

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Submitter Uwe Hermann
Date 2010-10-07 15:52:02
Message ID <20101007155202.GA12954@greenwood>
Download mbox | patch
Permalink /patch/2068/
State Accepted
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Comments

Uwe Hermann - 2010-10-07 15:52:02
See patch.


Uwe.
Stefan Reinauer - 2010-10-07 16:20:58
On 10/7/10 8:52 AM, Uwe Hermann wrote:
> v4_i82371eb_bootblock.patch
>
>
> Convert all Intel 82371AB/EB/MB based boards to TINY_BOOTBLOCK.
>
> Also:
>
> Unfortunately Intel 440BX + 82371AB/EB/MB boards can have their ISA device
> on various PCI bus:device.function locations.
> Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
>
> Thus, instead of hardcoding PCI bus:device.function numbers such as
> PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which
> works the same on all boards.
>
> As an additional benefit this patch also gets rid of one .c file include
> in romstage.c.
>
> Abuild-tested.
>
> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>

Acked-by: Stefan Reinauer <stepan@coresystems.de>
with one comment:

> Index: src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
> ===================================================================
> --- src/southbridge/intel/i82371eb/i82371eb_enable_rom.c	(Revision 5917)
> +++ src/southbridge/intel/i82371eb/i82371eb_enable_rom.c	(Arbeitskopie)
> -static void i82371eb_enable_rom(device_t dev)
> +static void i82371eb_enable_rom(void)
>  {
>  	u16 reg16;
> +	device_t dev;
>  
> +	/*
> +	 * Note: The Intel 82371AB/EB/MB ISA device can be on different
> +	 * PCI bus:device.function locations on different boards.
> +	 * Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
> +	 * But scanning for the PCI IDs (instead of hardcoding
> +	 * bus/device/function numbers) works on all boards.
> +	 */
> +	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
> +				       PCI_DEVICE_ID_INTEL_82371AB_ISA), 0);
> +
Does it make sense to use pci_locate_device_on_bus() here instead? Well,
maybe not because we start on bus 0 and the device is always there.
Maybe it's kind of too philosophical to distinguish.

Stefan
Uwe Hermann - 2010-10-07 17:33:33
On Thu, Oct 07, 2010 at 09:20:58AM -0700, Stefan Reinauer wrote:
> Acked-by: Stefan Reinauer <stepan@coresystems.de>

Thanks, r5918.


> > +	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
> > +				       PCI_DEVICE_ID_INTEL_82371AB_ISA), 0);
> > +
> Does it make sense to use pci_locate_device_on_bus() here instead? Well,
> maybe not because we start on bus 0 and the device is always there.
> Maybe it's kind of too philosophical to distinguish.

Hm, dunno. Maybe it saves some microseconds during boot or makes the
image slightly smaller? In that case it might make sense, but otherwise
it probably doesn't matter much.


Uwe.

Patch

Convert all Intel 82371AB/EB/MB based boards to TINY_BOOTBLOCK.

Also:

Unfortunately Intel 440BX + 82371AB/EB/MB boards can have their ISA device
on various PCI bus:device.function locations.
Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.

Thus, instead of hardcoding PCI bus:device.function numbers such as
PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which
works the same on all boards.

As an additional benefit this patch also gets rid of one .c file include
in romstage.c.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>

Index: src/southbridge/intel/i82371eb/Kconfig
===================================================================
--- src/southbridge/intel/i82371eb/Kconfig	(Revision 5917)
+++ src/southbridge/intel/i82371eb/Kconfig	(Arbeitskopie)
@@ -1,4 +1,10 @@ 
 config SOUTHBRIDGE_INTEL_I82371EB
 	bool
 	select IOAPIC
+	select TINY_BOOTBLOCK
 
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/intel/i82371eb/bootblock.c"
+	depends on SOUTHBRIDGE_INTEL_I82371EB
+
Index: src/southbridge/intel/i82371eb/bootblock.c
===================================================================
--- src/southbridge/intel/i82371eb/bootblock.c	(Revision 0)
+++ src/southbridge/intel/i82371eb/bootblock.c	(Revision 0)
@@ -0,0 +1,26 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
+
+static void bootblock_southbridge_init(void)
+{
+	i82371eb_enable_rom();
+}
Index: src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_enable_rom.c	(Revision 5917)
+++ src/southbridge/intel/i82371eb/i82371eb_enable_rom.c	(Arbeitskopie)
@@ -19,12 +19,26 @@ 
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
 #include "i82371eb.h"
 
-static void i82371eb_enable_rom(device_t dev)
+static void i82371eb_enable_rom(void)
 {
 	u16 reg16;
+	device_t dev;
 
+	/*
+	 * Note: The Intel 82371AB/EB/MB ISA device can be on different
+	 * PCI bus:device.function locations on different boards.
+	 * Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
+	 * But scanning for the PCI IDs (instead of hardcoding
+	 * bus/device/function numbers) works on all boards.
+	 */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
+				       PCI_DEVICE_ID_INTEL_82371AB_ISA), 0);
+
 	/* Enable access to the whole ROM, disable ROM write access. */
 	reg16 = pci_read_config16(dev, XBCS);
 	reg16 |= LOWER_BIOS_ENABLE;
Index: src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
===================================================================
--- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	(Revision 5917)
+++ src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -54,9 +53,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/a-trend/atc-6240/romstage.c
===================================================================
--- src/mainboard/a-trend/atc-6240/romstage.c	(Revision 5917)
+++ src/mainboard/a-trend/atc-6240/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/a-trend/atc-6220/romstage.c
===================================================================
--- src/mainboard/a-trend/atc-6220/romstage.c	(Revision 5917)
+++ src/mainboard/a-trend/atc-6220/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/gigabyte/ga-6bxc/romstage.c
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/romstage.c	(Revision 5917)
+++ src/mainboard/gigabyte/ga-6bxc/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -54,9 +53,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/gigabyte/ga-6bxe/romstage.c
===================================================================
--- src/mainboard/gigabyte/ga-6bxe/romstage.c	(Revision 5917)
+++ src/mainboard/gigabyte/ga-6bxe/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -55,9 +54,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/nokia/ip530/romstage.c
===================================================================
--- src/mainboard/nokia/ip530/romstage.c	(Revision 5917)
+++ src/mainboard/nokia/ip530/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0) ); /* ISA bridge at 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/biostar/m6tba/romstage.c
===================================================================
--- src/mainboard/biostar/m6tba/romstage.c	(Revision 5917)
+++ src/mainboard/biostar/m6tba/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -54,9 +53,6 @@ 
 	report_bist_failure(bist);
 	enable_smbus();
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	dump_spd_registers();
 	sdram_set_registers();
 	sdram_set_spd_registers();
Index: src/mainboard/azza/pt-6ibd/romstage.c
===================================================================
--- src/mainboard/azza/pt-6ibd/romstage.c	(Revision 5917)
+++ src/mainboard/azza/pt-6ibd/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -56,9 +55,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/tyan/s1846/romstage.c
===================================================================
--- src/mainboard/tyan/s1846/romstage.c	(Revision 5917)
+++ src/mainboard/tyan/s1846/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/abit/be6-ii_v2_0/romstage.c
===================================================================
--- src/mainboard/abit/be6-ii_v2_0/romstage.c	(Revision 5917)
+++ src/mainboard/abit/be6-ii_v2_0/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -56,9 +55,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge at 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
===================================================================
--- src/mainboard/compaq/deskpro_en_sff_p600/romstage.c	(Revision 5917)
+++ src/mainboard/compaq/deskpro_en_sff_p600/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -56,9 +55,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 14, 0)); /* ISA bridge is 00:14.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/msi/ms6119/romstage.c
===================================================================
--- src/mainboard/msi/ms6119/romstage.c	(Revision 5917)
+++ src/mainboard/msi/ms6119/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/msi/ms6147/romstage.c
===================================================================
--- src/mainboard/msi/ms6147/romstage.c	(Revision 5917)
+++ src/mainboard/msi/ms6147/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/msi/ms6156/romstage.c
===================================================================
--- src/mainboard/msi/ms6156/romstage.c	(Revision 5917)
+++ src/mainboard/msi/ms6156/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/asus/p2b-ls/romstage.c
===================================================================
--- src/mainboard/asus/p2b-ls/romstage.c	(Revision 5917)
+++ src/mainboard/asus/p2b-ls/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -55,9 +54,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/asus/p2b/romstage.c
===================================================================
--- src/mainboard/asus/p2b/romstage.c	(Revision 5917)
+++ src/mainboard/asus/p2b/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/asus/p2b-d/romstage.c
===================================================================
--- src/mainboard/asus/p2b-d/romstage.c	(Revision 5917)
+++ src/mainboard/asus/p2b-d/romstage.c	(Arbeitskopie)
@@ -27,7 +27,6 @@ 
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -56,9 +55,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/asus/p2b-f/romstage.c
===================================================================
--- src/mainboard/asus/p2b-f/romstage.c	(Revision 5917)
+++ src/mainboard/asus/p2b-f/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -56,9 +55,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/asus/p2b-ds/romstage.c
===================================================================
--- src/mainboard/asus/p2b-ds/romstage.c	(Revision 5917)
+++ src/mainboard/asus/p2b-ds/romstage.c	(Arbeitskopie)
@@ -27,7 +27,6 @@ 
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -56,9 +55,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
Index: src/mainboard/asus/p3b-f/romstage.c
===================================================================
--- src/mainboard/asus/p3b-f/romstage.c	(Revision 5917)
+++ src/mainboard/asus/p3b-f/romstage.c	(Arbeitskopie)
@@ -26,7 +26,6 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_pm.c"
 #include "northbridge/intel/i440bx/raminit.h"
@@ -88,9 +87,6 @@ 
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
-
 	enable_smbus();
 	enable_pm();