===================================================================
@@ -13,6 +13,7 @@
#define CPU_REV_2_1 0x021
#define CPU_REV_2_2 0x022
#define CPU_REV_3_0 0x030
+
/* GeodeLink Control Processor Registers, GLIU1, Port 3 */
#define GLCP_CLK_DIS_DELAY 0x4c000008
#define GLCP_PMCLKDISABLE 0x4c000009
@@ -43,7 +44,7 @@
/* next3 bits next port if through an GLIU*/
/* etc...*/
-/*Redcloud as follows.*/
+/* Redcloud as follows.*/
/* GLIU0*/
/* port0 - GLIU0*/
/* port1 - MC*/
@@ -59,7 +60,6 @@
/* port4 - PCI*/
/* port5 - FG*/
-
#define GL0_GLIU0 0
#define GL0_MC 1
#define GL0_GLIU1 2
@@ -88,14 +88,11 @@
#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */
#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */
#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */
+
/* South Bridge*/
#define SB_PORT 2 /* port of the SouthBridge */
-
-/**/
-/*GeodeLink Interface Unit 0 (GLIU0) port0*/
-/**/
-
+/* GeodeLink Interface Unit 0 (GLIU0) port0*/
#define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000)
#define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004)
@@ -103,10 +100,7 @@
#define GLIU0_CAP (MSR_GLIU0 + 0x86)
#define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80)
-
-/**/
/* Memory Controller GLIU0 port 1*/
-/**/
#define MC_GLD_MSR_CAP (MSR_MC + 0x2000)
#define MC_GLD_MSR_PM (MSR_MC + 0x2004)
@@ -129,7 +123,6 @@
#define CF07_LOWER_REF_TEST_SET (1 << 3)
#define CF07_LOWER_PROG_DRAM_SET (1 << 0)
-
#define MC_CF8F_DATA (MSR_MC + 0x19)
#define CF8F_UPPER_XOR_BS_SHIFT 19
@@ -164,19 +157,13 @@
#define MC_CF_RDSYNC (MSR_MC + 0x1F)
-
-/**/
/* GLIU1 GLIU0 port2*/
-/**/
#define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000)
#define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004)
#define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80)
-
-/**/
/* CPU ; does not need routing instructions since we are executing there.*/
-/**/
#define CPU_GLD_MSR_CAP 0x2000
#define CPU_GLD_MSR_CONFIG 0x2001
#define CPU_GLD_MSR_PM 0x2004
@@ -200,7 +187,7 @@
#define CPU_AC_MSR 0x1301
#define CPU_EX_BIST 0x1428
-/*IM*/
+/* IM*/
#define CPU_IM_CONFIG 0x1700
#define IM_CONFIG_LOWER_ICD_SET (1 << 8)
#define IM_CONFIG_LOWER_QWT_SET (1 << 20)
@@ -215,13 +202,13 @@
#define CPU_IM_BIST_TAG 0x1730
#define CPU_IM_BIST_DATA 0x1731
-
/* various CPU MSRs */
#define CPU_DM_CONFIG0 0x1800
#define DM_CONFIG0_UPPER_WSREQ_SHIFT 12
#define DM_CONFIG0_LOWER_DCDIS_SET (1<<8)
#define DM_CONFIG0_LOWER_WBINVD_SET (1<<5)
#define DM_CONFIG0_LOWER_MISSER_SET (1<<1)
+
/* configuration MSRs */
#define CPU_RCONF_DEFAULT 0x1808
#define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24
@@ -294,10 +281,7 @@
#define TSC_SUSP_SET (1<<5)
#define SUSP_EN_SET (1<<12)
- /**/
- /* VG GLIU0 port4*/
- /**/
-
+/* VG GLIU0 port4*/
#define VG_GLD_MSR_CAP (MSR_VG + 0x2000)
#define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001)
#define VG_GLD_MSR_PM (MSR_VG + 0x2004)
@@ -306,22 +290,13 @@
#define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001)
#define GP_GLD_MSR_PM (MSR_GP + 0x2004)
-
-
-/**/
-/* DF GLIU0 port6*/
-/**/
-
+/* DF GLIU0 port6*/
#define DF_GLD_MSR_CAP (MSR_DF + 0x2000)
#define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001)
#define DF_LOWER_LCD_SHIFT 6
#define DF_GLD_MSR_PM (MSR_DF + 0x2004)
-
-
-/**/
/* GeodeLink Control Processor GLIU1 port3*/
-/**/
#define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000)
#define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001)
#define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004)
@@ -355,10 +330,7 @@
#define GLCP_DOTPLL (MSR_GLCP + 0x15 /* R/W*/)
#define DOTPPL_LOWER_PD_SET (1<<14)
-
-/**/
-/* GLIU1 port 4*/
-/**/
+/* GLIU1 port 4*/
#define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000)
#define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001)
#define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004)
@@ -423,27 +395,30 @@
#define GLPCI_SPARE_LOWER_NSE_SET (1<<1)
#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
-
-/**/
/* FooGlue GLIU1 port 5*/
-/**/
#define FG_GLD_MSR_CAP (MSR_FG + 0x2000)
#define FG_GLD_MSR_PM (MSR_FG + 0x2004)
-/* VIP GLIU1 port 5*/
-/* */
+/* VIP GLIU1 port 5*/
#define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000)
#define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001)
#define VIP_GLD_MSR_PM (MSR_VIP + 0x2004)
#define VIP_BIST (MSR_VIP + 0x2005)
#define VIP_GIO_MSR_SEL (MSR_VIP + 0x2010)
-/* */
-/* AES GLIU1 port 6*/
-/* */
+
+/* AES GLIU1 port 6*/
#define AES_GLD_MSR_CAP (MSR_AES + 0x2000)
#define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001)
#define AES_GLD_MSR_PM (MSR_AES + 0x2004)
#define AES_CONTROL (MSR_AES + 0x2006)
+
+/* from MC spec */
+#define MIN_MOD_BANKS 1
+#define MAX_MOD_BANKS 2
+#define MIN_DEV_BANKS 2
+#define MAX_DEV_BANKS 4
+#define MAX_COL_ADDR 17
+
/* more fun stuff */
#define BM 1 /* Base Mask - map power of 2 size aligned region*/
#define BMO 2 /* BM with an offset*/
@@ -465,8 +440,8 @@
#define MSR_GL0 (GL1_GLIU0 << 29)
-/* Set up desc addresses from 20 - 3f*/
-/* This is chip specific!*/
+/* Set up desc addresses from 20 - 3f*/
+/* This is chip specific!*/
#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM*/
#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM*/
#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/
@@ -503,9 +478,7 @@
#define CHIPSET_DEV_NUM 15
#define IDSEL_BASE 11 // bit 11 = device 1
-/* */
/* SB LBAR IO + MEMORY MAP*/
-/* */
#define SMBUS_BASE ( 0x6000)
#define GPIO_BASE ( 0x6100)
#define MFGPT_BASE ( 0x6200)
===================================================================
@@ -34,92 +34,21 @@
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
+#define DIMM0 0xA0
+#define DIMM1 0xA2
-#include "northbridge/amd/gx2/raminit.h"
-
- /* This is needed because ROMCC doesn`t now the ctz bitop */
-static inline unsigned int ctz(unsigned int n)
+static inline int spd_read_byte(unsigned int device, unsigned int address)
{
- int zeros;
+ if (device != DIMM0)
+ return 0xFF; /* No DIMM1, don't even try. */
- n = (n ^ (n - 1)) >> 1;
- for (zeros = 0; n; zeros++)
- {
- n >>= 1;
- }
- return zeros;
+ return smbus_read_byte(device, address);
}
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
-{
- /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
- * component Banks (byte 17) * module banks, side (byte 5) *
- * width in bits (byte 6,7)
- * = Density per side (byte 31) * number of sides (byte 5) */
- /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
- msr_t msr;
- unsigned char module_banks, val;
- uint16_t dimm_size;
-
- msr = rdmsr(MC_CF07_DATA);
-
- /* get module banks (sides) per dimm, SPD byte 5 */
- module_banks = spd_read_byte(0xA0, 5);
- if (module_banks < 1 || module_banks > 2)
- print_err("Module banks per dimm\n");
- module_banks >>= 1;
- msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
- msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
-
- /* get component banks per module bank, SPD byte 17 */
- val = spd_read_byte(0xA0, 17);
- if (val < 2 || val > 4)
- print_err("Component banks per module bank\n");
- val >>= 2;
- msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
- msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
-
- dimm_size = spd_read_byte(0xA0, 31);
- dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
- dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
- /* Module Density * Module Banks */
- dimm_size <<= (0 >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
- if (dimm_size != 0) {
- dimm_size = ctz(dimm_size);
- }
- if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */
- print_err("Only support up to 512MB \n");
- hlt();
- }
- msr.hi |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
-
- /* page size = 2^col address */
- val = spd_read_byte(0xA0, 4);
- val -= 7;
- msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
- msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
-
- print_debug("computed msr.hi ");
- print_debug_hex32(msr.hi);
- print_debug("\n");
-
- msr.lo = 0x00003400;
- wrmsr(MC_CF07_DATA, msr);
-
- msr = rdmsr(MC_CF8F_DATA);
- msr.hi = 0x18000008;
- msr.lo = 0x296332a3;
- wrmsr(MC_CF8F_DATA, msr);
-
-}
-
+#include "northbridge/amd/gx2/raminit.h"
+#include "northbridge/amd/gx2/pll_reset.c"
#include "northbridge/amd/gx2/raminit.c"
#include "lib/generic_sdram.c"
-#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
===================================================================
@@ -15,87 +15,21 @@
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#define DIMM0 0xA0
+#define DIMM1 0xA2
+
static inline int spd_read_byte(unsigned device, unsigned address)
{
- return smbus_read_byte(device, address);
-}
+ if (device != DIMM0)
+ return 0xFF; /* No DIMM1, don't even try. */
-#include "northbridge/amd/gx2/raminit.h"
-
-static inline unsigned int fls(unsigned int x)
-{
- int r;
-
- __asm__("bsfl %1,%0\n\t"
- "jnz 1f\n\t"
- "movl $32,%0\n"
- "1:" : "=r" (r) : "g" (x));
- return r;
+ return smbus_read_byte(device, address);
}
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
-{
- /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
- * component Banks (byte 17) * module banks, side (byte 5) *
- * width in bits (byte 6,7)
- * = Density per side (byte 31) * number of sides (byte 5) */
- /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
- msr_t msr;
- unsigned char module_banks, val;
-
- msr = rdmsr(MC_CF07_DATA);
-
- /* get module banks (sides) per dimm, SPD byte 5 */
- module_banks = spd_read_byte(0xA0, 5);
- if (module_banks < 1 || module_banks > 2)
- print_err("Module banks per dimm\n");
- module_banks >>= 1;
- msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
- msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
-
- /* get component banks per module bank, SPD byte 17 */
- val = spd_read_byte(0xA0, 17);
- if (val < 2 || val > 4)
- print_err("Component banks per module bank\n");
- val >>= 2;
- msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
- msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
-
- /* get the module bank density, SPD byte 31 */
- val = spd_read_byte(0xA0, 31);
- val = fls(val);
- val <<= module_banks;
- msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT);
- msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT);
-
- /* page size = 2^col address */
- val = spd_read_byte(0xA0, 4);
- val -= 7;
- msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
- msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
-
- print_debug("computed msr.hi ");
- print_debug_hex32(msr.hi);
- print_debug("\n");
-
- msr.lo = 0x00003000;
- wrmsr(MC_CF07_DATA, msr);
-
- msr = rdmsr(0x20000019);
- msr.hi = 0x18000108;
- msr.lo = 0x696332a3;
- wrmsr(0x20000019, msr);
-
-}
-
+#include "northbridge/amd/gx2/raminit.h"
+#include "northbridge/amd/gx2/pll_reset.c"
#include "northbridge/amd/gx2/raminit.c"
#include "lib/generic_sdram.c"
-
-#define PLLMSRhi 0x00001490
-#define PLLMSRlo 0x02000030
-#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
-#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
-#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
===================================================================
@@ -6,6 +6,7 @@
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5535
+ select HAVE_DEBUG_SMBUS
select UDELAY_TSC
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
===================================================================
@@ -1,4 +1,5 @@
#include <stdint.h>
+#include <spd.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -15,35 +16,61 @@
#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
#include "southbridge/amd/cs5535/cs5535_early_setup.c"
-#include "northbridge/amd/gx2/raminit.h"
-/* this has to be done on a per-mainboard basis, esp. if you don't have smbus */
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+#define DIMM0 0xA0
+#define DIMM1 0xA2
+
+static const unsigned char spdbytes[] = { /* 4x Qimonda HYB25DC512160CF-6 */
+ 0xFF, 0xFF, /* only values used by raminit.c are set */
+ [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, /* (Fundamental) memory type */
+ [SPD_NUM_ROWS] = 0x0D, /* Number of row address bits [13] */
+ [SPD_NUM_COLUMNS] = 0x0A, /* Number of column address bits [10] */
+ [SPD_NUM_DIMM_BANKS] = 1, /* Number of module rows (banks) */
+ 0xFF, 0xFF, 0xFF,
+ [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x60, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [6.0 ns in BCD] */
+ 0xFF, 0xFF,
+ [SPD_REFRESH] = 0x82, /* Refresh rate/type [Self Refresh, 7.8 us] */
+ [SPD_PRIMARY_SDRAM_WIDTH] = 64, /* SDRAM width (primary SDRAM) [64 bits] */
+ 0xFF, 0xFF, 0xFF,
+ [SPD_NUM_BANKS_PER_SDRAM] = 4, /* SDRAM device attributes, number of banks on SDRAM device */
+ [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x1C, /* SDRAM device attributes, CAS latency [3, 2.5, 2] */
+ 0xFF, 0xFF,
+ [SPD_MODULE_ATTRIBUTES] = 0x20, /* SDRAM module attributes [differential clk] */
+ [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, /* SDRAM device attributes, general [Concurrent AP] */
+ [SPD_SDRAM_CYCLE_TIME_2ND] = 0x60, /* SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD] */
+ 0xFF,
+ [SPD_SDRAM_CYCLE_TIME_3RD] = 0x75, /* SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD] */
+ 0xFF,
+ [SPD_tRP] = 72, /* Min. row precharge time [18 ns in units of 0.25 ns] */
+ [SPD_tRRD] = 48, /* Min. row active to row active [12 ns in units of 0.25 ns] */
+ [SPD_tRCD] = 72, /* Min. RAS to CAS delay [18 ns in units of 0.25 ns] */
+ [SPD_tRAS] = 42, /* Min. RAS pulse width = active to precharge delay [42 ns] */
+ [SPD_BANK_DENSITY] = 0x40, /* Density of each row on module [256 MB] */
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ [SPD_tRFC] = 72 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [72 ns] */
+};
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
{
- msr_t msr;
- /* 1. Initialize GLMC registers base on SPD values,
- * Hard coded as XpressROM for now */
- //print_debug("sdram_enable step 1\n");
- msr = rdmsr(0x20000018);
- msr.hi = 0x10076013;
- msr.lo = 0x3400;
- wrmsr(0x20000018, msr);
+ if (device != DIMM0)
+ return 0xFF; /* No DIMM1, don't even try. */
- msr = rdmsr(0x20000019);
- msr.hi = 0x18000008;
- msr.lo = 0x696332a3;
- wrmsr(0x20000019, msr);
+#if CONFIG_DEBUG_SMBUS
+ if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
+ print_err("ERROR: spd_read_byte(DIMM0, 0x");
+ print_err_hex8(address);
+ print_err(") returns 0xff\n");
+ }
+#endif
+ /* Fake SPD ROM value */
+ return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF;
}
+#include "northbridge/amd/gx2/raminit.h"
+#include "northbridge/amd/gx2/pll_reset.c"
#include "northbridge/amd/gx2/raminit.c"
#include "lib/generic_sdram.c"
-
-#define PLLMSRhi 0x00000226
-#define PLLMSRlo 0x00000008
-#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
-#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
-#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
===================================================================
@@ -21,3 +21,9 @@
bool
select GEODE_VSA
+# Valid PROCESSOR_MHZ options: 300 ; 366 ; 400 Mhz
+config PROCESSOR_MHZ
+ int
+ default 366
+ depends on NORTHBRIDGE_AMD_GX2
+
===================================================================
@@ -1,9 +1,523 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Nils Jacobs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
#include <cpu/amd/gx2def.h>
+#include <spd.h>
+static const unsigned char NumColAddr[] = {
+ 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
+};
+
+static void banner(const char *s)
+{
+ printk(BIOS_DEBUG, " * %s\n", s);
+}
+
+static void hcf(void)
+{
+ print_emerg("DIE\n");
+ /* this guarantees we flush the UART fifos (if any) and also
+ * ensures that things, in general, keep going so no debug output
+ * is lost
+ */
+ while (1)
+ print_emerg_char(0);
+}
+
+static void auto_size_dimm(unsigned int dimm)
+{
+ uint32_t dimm_setting;
+ uint16_t dimm_size;
+ uint8_t spd_byte;
+ msr_t msr;
+
+ dimm_setting = 0;
+
+ banner("Check present");
+ /* Check that we have a dimm */
+ if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
+ return;
+ }
+
+ banner("MODBANKS");
+ /* Field: Module Banks per DIMM */
+ /* EEPROM byte usage: (5) Number of DIMM Banks */
+ spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
+ if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
+ print_emerg("Number of module banks not compatible\n");
+ post_code(ERROR_BANK_SET);
+ hcf();
+ }
+ dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
+ banner("FIELDBANKS");
+
+ /* Field: Banks per SDRAM device */
+ /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
+ spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
+ if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
+ print_emerg("Number of device banks not compatible\n");
+ post_code(ERROR_BANK_SET);
+ hcf();
+ }
+ dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
+ banner("SPDNUMROWS");
+
+ /*; Field: DIMM size
+ *; EEPROM byte usage: (3) Number of Row Addresses
+ *; (4) Number of Column Addresses
+ *; (5) Number of DIMM Banks
+ *; (31) Module Bank Density
+ *; Size = Module Density * Module Banks
+ */
+ if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
+ || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
+ print_emerg("Assymetirc DIMM not compatible\n");
+ post_code(ERROR_UNSUPPORTED_DIMM);
+ hcf();
+ }
+ banner("SPDBANKDENSITY");
+
+ dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
+ banner("DIMMSIZE");
+ dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
+ dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
+
+ /* Module Density * Module Banks */
+ dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
+ banner("BEFORT CTZ");
+ dimm_size = __builtin_ctz(dimm_size);
+ banner("TEST DIMM SIZE>7");
+ if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */
+ print_emerg("Only support up to 512MB per DIMM\n");
+ post_code(ERROR_DENSITY_DIMM);
+ hcf();
+ }
+ dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
+ banner("PAGESIZE");
+
+/*; Field: PAGE size
+*; EEPROM byte usage: (4) Number of Column Addresses
+*; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
+*
+*; But this really works by magic.
+*; If ma[11:0] is the memory address pins, and pa[13:0] is the physical column address
+*; that MC generates, here is how the MC assigns the pa onto the ma pins:
+*
+*;ma 11 10 09 08 07 06 05 04 03 02 01 00
+*;--------------------------------------------------------------------------------------------------------------------------------------
+*;pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size)
+*;pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size)
+*;pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size)
+*;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)
+*;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)
+*; *AP=autoprecharge bit
+*
+*; Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
+*; so lower 3 address bits are dont_cares.So from the table above,
+*; it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h),
+*; it adds 3 to get 10, then does 2^10=1K. Get it?*/
+
+ spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
+ banner("MAXCOLADDR");
+ if (spd_byte > MAX_COL_ADDR) {
+ print_emerg("DIMM page size not compatible\n");
+ post_code(ERROR_SET_PAGE);
+ hcf();
+ }
+ banner(">11address test");
+ spd_byte -= 7;
+ if (spd_byte > 4) { /* if the value is above 4 it means >11 col address lines */
+ spd_byte = 7; /* which means >16k so set to disabled */
+ }
+ dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
+
+ banner("RDMSR CF07");
+ msr = rdmsr(MC_CF07_DATA);
+ banner("WRMSR CF07");
+ if (dimm == DIMM0) {
+ msr.hi &= 0xFFFF0000;
+ msr.hi |= dimm_setting;
+ } else {
+ msr.hi &= 0x0000FFFF;
+ msr.hi |= dimm_setting << 16;
+ }
+ wrmsr(MC_CF07_DATA, msr);
+ banner("ALL DONE");
+}
+
+static void checkDDRMax(void)
+{
+ uint8_t spd_byte0, spd_byte1;
+ uint16_t speed;
+
+ /* PC133 identifier */
+ spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
+ if (spd_byte0 == 0xFF) {
+ spd_byte0 = 0;
+ }
+ spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
+ if (spd_byte1 == 0xFF) {
+ spd_byte1 = 0;
+ }
+
+ /* Use the slowest DIMM */
+ if (spd_byte0 < spd_byte1) {
+ spd_byte0 = spd_byte1;
+ }
+
+ /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+ speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));
+
+ /* current speed > max speed? */
+ if (GeodeLinkSpeed() > speed) {
+ print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
+ post_code(POST_PLL_MEM_FAIL);
+ hcf();
+ }
+}
+
+const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
+
+static void set_refresh_rate(void)
+{
+ uint8_t spd_byte0, spd_byte1;
+ uint16_t rate0, rate1;
+ msr_t msr;
+
+ spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);
+ spd_byte0 &= 0xF;
+ if (spd_byte0 > 5) {
+ spd_byte0 = 5;
+ }
+ rate0 = REF_RATE[spd_byte0];
+
+ spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);
+ spd_byte1 &= 0xF;
+ if (spd_byte1 > 5) {
+ spd_byte1 = 5;
+ }
+ rate1 = REF_RATE[spd_byte1];
+
+ /* Use the faster rate (lowest number) */
+ if (rate0 > rate1) {
+ rate0 = rate1;
+ }
+
+ msr = rdmsr(MC_CF07_DATA);
+ msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
+ << CF07_LOWER_REF_INT_SHIFT;
+ wrmsr(MC_CF07_DATA, msr);
+}
+
+const uint8_t CASDDR[] = { 5, 5, 2, 6, 0 }; /* 1(1.5), 1.5, 2, 2.5, 0 */
+
+static u8 getcasmap(u32 dimm, u16 glspeed)
+{
+ u16 dimm_speed;
+ u8 spd_byte, casmap, casmap_shift=0;
+
+ /************************** DIMM0 **********************************/
+ casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);
+ if (casmap != 0xFF) {
+ /* IF -.5 timing is supported, check -.5 timing > GeodeLink */
+ spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);
+ if (spd_byte != 0) {
+ /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+ dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
+ if (dimm_speed >= glspeed) {
+ casmap_shift = 1; /* -.5 is a shift of 1 */
+ /* IF -1 timing is supported, check -1 timing > GeodeLink */
+ spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);
+ if (spd_byte != 0) {
+ /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+ dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
+ if (dimm_speed >= glspeed) {
+ casmap_shift = 2; /* -1 is a shift of 2 */
+ }
+ } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
+ } else {
+ casmap_shift = 0;
+ }
+ } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
+ /* set the casmap based on the shift to limit possible CAS settings */
+ spd_byte = 31 - __builtin_clz((uint32_t) casmap);
+ /* just want bits in the lower byte since we have to cast to a 32 */
+ casmap &= 0xFF << (spd_byte - casmap_shift);
+ } else { /* No DIMM */
+ casmap = 0;
+ }
+ return casmap;
+}
+
+static void setCAS(void)
+{
+/*;*****************************************************************************
+;*
+;* setCAS
+;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency
+;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
+;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
+;*
+;* The CAS setting is based on the information provided in each DIMMs SPD.
+;* The speed at which a DIMM can run is described relative to the slowest
+;* CAS the DIMM supports. Each speed for the relative CAS settings is
+;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
+;* speed, the CAS setting is removed from the list of good settings for
+;* the DIMM. This is done for both DIMMs and the lists are compared to
+;* find the lowest common CAS latency setting. If there are no CAS settings
+;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
+;*
+;* Entry:
+;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
+;* Destroys: We really use everything !
+;*****************************************************************************/
+ uint16_t glspeed;
+ uint8_t spd_byte, casmap0, casmap1;
+ msr_t msr;
+
+ glspeed = GeodeLinkSpeed();
+
+ casmap0 = getcasmap(DIMM0, glspeed);
+ casmap1 = getcasmap(DIMM1, glspeed);
+
+ /********************* CAS_LAT MAP COMPARE ***************************/
+ if (casmap0 == 0) {
+ spd_byte = CASDDR[__builtin_ctz(casmap1)];
+ } else if (casmap1 == 0) {
+ spd_byte = CASDDR[__builtin_ctz(casmap0)];
+ } else if ((casmap0 &= casmap1)) {
+ spd_byte = CASDDR[__builtin_ctz(casmap0)];
+ } else {
+ print_emerg("DIMM CAS Latencies not compatible\n");
+ post_code(ERROR_DIFF_DIMMS);
+ hcf();
+ }
+
+ msr = rdmsr(MC_CF8F_DATA);
+ msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
+ msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;
+ wrmsr(MC_CF8F_DATA, msr);
+}
+
+static void set_latencies(void)
+{
+ uint32_t memspeed, dimm_setting;
+ uint8_t spd_byte0, spd_byte1;
+ msr_t msr;
+
+ memspeed = GeodeLinkSpeed() / 2;
+ dimm_setting = 0;
+
+ /* MC_CF8F setup */
+ /* tRAS */
+ spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);
+ if (spd_byte0 == 0xFF) {
+ spd_byte0 = 0;
+ }
+ spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);
+ if (spd_byte1 == 0xFF) {
+ spd_byte1 = 0;
+ }
+ if (spd_byte0 < spd_byte1) {
+ spd_byte0 = spd_byte1;
+ }
+ /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+ spd_byte1 = (spd_byte0 * memspeed) / 1000;
+ if (((spd_byte0 * memspeed) % 1000)) {
+ ++spd_byte1;
+ }
+ if (spd_byte1 > 6) {
+ --spd_byte1;
+ }
+ dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
+
+ /* tRP */
+ spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);
+ if (spd_byte0 == 0xFF) {
+ spd_byte0 = 0;
+ }
+ spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);
+ if (spd_byte1 == 0xFF) {
+ spd_byte1 = 0;
+ }
+ if (spd_byte0 < spd_byte1) {
+ spd_byte0 = spd_byte1;
+ }
+ /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+ spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
+ if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
+ ++spd_byte1;
+ }
+ dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
+
+ /* tRCD */
+ spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);
+ if (spd_byte0 == 0xFF) {
+ spd_byte0 = 0;
+ }
+ spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);
+ if (spd_byte1 == 0xFF) {
+ spd_byte1 = 0;
+ }
+ if (spd_byte0 < spd_byte1) {
+ spd_byte0 = spd_byte1;
+ }
+ /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+ spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
+ if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
+ ++spd_byte1;
+ }
+ dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
+
+ /* tRRD */
+ spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);
+ if (spd_byte0 == 0xFF) {
+ spd_byte0 = 0;
+ }
+ spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);
+ if (spd_byte1 == 0xFF) {
+ spd_byte1 = 0;
+ }
+ if (spd_byte0 < spd_byte1) {
+ spd_byte0 = spd_byte1;
+ }
+ /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+ spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
+ if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
+ ++spd_byte1;
+ }
+ dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
+
+ /* tRC = tRP + tRAS */
+ dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
+ ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
+ << CF8F_LOWER_REF2ACT_SHIFT;
+
+ msr = rdmsr(MC_CF8F_DATA);
+ msr.lo &= 0xF00000FF;
+ msr.lo |= dimm_setting;
+ msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
+ wrmsr(MC_CF8F_DATA, msr);
+ printk(BIOS_DEBUG, "MSR MC_CF8F_DATA (%08x) value is %08x:%08x\n",
+ MC_CF8F_DATA, msr.hi, msr.lo);
+}
+
+static void set_extended_mode_registers(void)
+{
+ uint8_t spd_byte0, spd_byte1;
+ msr_t msr;
+ spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);
+ if (spd_byte0 == 0xFF) {
+ spd_byte0 = 0;
+ }
+ spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);
+ if (spd_byte1 == 0xFF) {
+ spd_byte1 = 0;
+ }
+ spd_byte1 &= spd_byte0;
+
+ msr = rdmsr(MC_CF07_DATA);
+ if (spd_byte1 & 1) { /* Drive Strength Control */
+ msr.lo |= CF07_LOWER_EMR_DRV_SET;
+ }
+ if (spd_byte1 & 2) { /* FET Control */
+ msr.lo |= CF07_LOWER_EMR_QFC_SET;
+ }
+ wrmsr(MC_CF07_DATA, msr);
+}
+
static void sdram_set_registers(const struct mem_controller *ctrl)
{
+ msr_t msr;
+ uint32_t msrnum;
+
+ /* Set Refresh Staggering */
+ msrnum = MC_CF07_DATA;
+ msr = rdmsr(msrnum);
+ msr.lo &= ~0xC0;
+ msr.lo |= 0x0; /* set refresh to 4SDRAM clocks */
+ wrmsr(msrnum, msr);
+
+ /* Memory Interleave: Set HOI here otherwise default is LOI */
+ /* msrnum = MC_CF8F_DATA;
+ msr = rdmsr(msrnum);
+ msr.hi |= CF8F_UPPER_HOI_LOI_SET;
+ wrmsr(msrnum, msr); */
}
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+{
+ uint8_t spd_byte;
+
+ banner("sdram_set_spd_register");
+ post_code(POST_MEM_SETUP); // post_70h
+
+ spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
+ banner("Check DIMM 0");
+ /* Check DIMM is not Register and not Buffered DIMMs. */
+ if ((spd_byte != 0xFF) && (spd_byte & 3)) {
+ print_emerg("DIMM0 NOT COMPATIBLE\n");
+ post_code(ERROR_UNSUPPORTED_DIMM);
+ hcf();
+ }
+ banner("Check DIMM 1");
+ spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
+ if ((spd_byte != 0xFF) && (spd_byte & 3)) {
+ print_emerg("DIMM1 NOT COMPATIBLE\n");
+ post_code(ERROR_UNSUPPORTED_DIMM);
+ hcf();
+ }
+
+ post_code(POST_MEM_SETUP2); // post_72h
+ banner("Check DDR MAX");
+
+ /* Check that the memory is not overclocked. */
+ checkDDRMax();
+
+ /* Size the DIMMS */
+ post_code(POST_MEM_SETUP3); // post_73h
+ banner("AUTOSIZE DIMM 0");
+ auto_size_dimm(DIMM0);
+ post_code(POST_MEM_SETUP4); // post_74h
+ banner("AUTOSIZE DIMM 1");
+ auto_size_dimm(DIMM1);
+
+ /* Set CAS latency */
+ banner("set cas latency");
+ post_code(POST_MEM_SETUP5); // post_75h
+ setCAS();
+
+ /* Set all the other latencies here (tRAS, tRP....) */
+ banner("set all latency");
+ set_latencies();
+
+ /* Set Extended Mode Registers */
+ banner("set emrs");
+ set_extended_mode_registers();
+
+ banner("set ref rate");
+ /* Set Memory Refresh Rate */
+ set_refresh_rate();
+}
+
/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
@@ -12,70 +526,58 @@
msr_t msr;
/* 2. clock gating for PMode */
- msr = rdmsr(0x20002004);
+ msr = rdmsr(MC_GLD_MSR_PM);
msr.lo &= ~0x04;
msr.lo |= 0x01;
- wrmsr(0x20002004, msr);
+ wrmsr(MC_GLD_MSR_PM, msr);
/* undocmented bits in GX, in LX there are
* 8 bits in PM1_UP_DLY */
- msr = rdmsr(0x2000001a);
+ msr = rdmsr(MC_CF1017_DATA);
msr.lo = 0x0101;
- wrmsr(0x2000001a, msr);
+ wrmsr(MC_CF1017_DATA, msr);
//print_debug("sdram_enable step 2\n");
/* 3. release CKE mask to enable CKE */
- msr = rdmsr(0x2000001d);
+ msr = rdmsr(MC_CFCLK_DBUG);
msr.lo &= ~(0x03 << 8);
- wrmsr(0x2000201d, msr);
+ wrmsr(MC_CFCLK_DBUG, msr);
//print_debug("sdram_enable step 3\n");
/* 4. set and clear REF_TST 16 times, more shouldn't hurt
* why this is before EMRS and MRS ? */
for (i = 0; i < 19; i++) {
- msr = rdmsr(0x20000018);
+ msr = rdmsr(MC_CF07_DATA);
msr.lo |= (0x01 << 3);
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
msr.lo &= ~(0x01 << 3);
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
}
//print_debug("sdram_enable step 4\n");
- /* 5. set refresh interval */
- msr = rdmsr(0x20000018);
- msr.lo &= ~(0xffff << 8);
- msr.lo |= (0x34 << 8);
- wrmsr(0x20000018, msr);
- /* set refresh staggering to 4 SDRAM clocks */
- msr = rdmsr(0x20000018);
- msr.lo &= ~(0x03 << 6);
- msr.lo |= (0x00 << 6);
- wrmsr(0x20000018, msr);
- //print_debug("sdram_enable step 5\n");
-
/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
- msr = rdmsr(0x20000018);
+ msr = rdmsr(MC_CF07_DATA);
msr.lo |= ((0x01 << 28) | 0x01);
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
msr.lo &= ~((0x01 << 28) | 0x01);
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
//print_debug("sdram_enable step 6\n");
/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
* it is documented in LX datasheet */
/* load Mode Register by set and clear PROG_DRAM */
- msr = rdmsr(0x20000018);
+ msr = rdmsr(MC_CF07_DATA);
msr.lo |= ((0x01 << 27) | 0x01);
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
msr.lo &= ~((0x01 << 27) | 0x01);
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
//print_debug("sdram_enable step 7\n");
/* 8. load Mode Register by set and clear PROG_DRAM */
- msr = rdmsr(0x20000018);
+ msr = rdmsr(MC_CF07_DATA);
msr.lo |= 0x01;
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
msr.lo &= ~0x01;
- wrmsr(0x20000018, msr);
+ wrmsr(MC_CF07_DATA, msr);
//print_debug("sdram_enable step 8\n");
/* wait 200 SDCLKs */
@@ -83,7 +585,7 @@
outb(0xaa, 0x80);
/* load RDSYNC */
- msr = rdmsr(0x2000001f);
+ msr = rdmsr(MC_CF_RDSYNC);
msr.hi = 0x000ff310;
/* the above setting is supposed to be good for "slow" ram. We have found that for
* some dram, at some clock rates, e.g. hynix at 366/244, this will actually
@@ -94,13 +596,13 @@
*/
msr.hi = 0x00000310;
msr.lo = 0x00000000;
- wrmsr(0x2000001f, msr);
+ wrmsr(MC_CF_RDSYNC, msr);
/* set delay control */
- msr = rdmsr(0x4c00000f);
+ msr = rdmsr(GLCP_DELAY_CONTROLS);
msr.hi = 0x830d415a;
msr.lo = 0x8ea0ad6a;
- wrmsr(0x4c00000f, msr);
+ wrmsr(GLCP_DELAY_CONTROLS, msr);
/* The RAM dll needs a write to lock on so generate a few dummy writes */
/* Note: The descriptor needs to be enabled to point at memory */
===================================================================
@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Nils Jacobs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
#include <cpu/x86/tsc.h>
#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */
@@ -4,72 +24,9 @@
#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */
#define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */
-#if 0
-static unsigned int calibrate_tsc(void)
-{
- /* Set the Gate high, disable speaker */
- outb((inb(0x61) & ~0x02) | 0x01, 0x61);
-
- /*
- * Now let's take care of CTC channel 2
- *
- * Set the Gate high, program CTC channel 2 for mode 0,
- * (interrupt on terminal count mode), binary count,
- * load 5 * LATCH count, (LSB and MSB) to begin countdown.
- */
- outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
- outb(CALIBRATE_INTERVAL & 0xff, 0x42); /* LSB of count */
- outb(CALIBRATE_INTERVAL >> 8, 0x42); /* MSB of count */
-
- {
- tsc_t start;
- tsc_t end;
- unsigned long count;
-
- start = rdtsc();
- count = 0;
- do {
- count++;
- } while ((inb(0x61) & 0x20) == 0);
- end = rdtsc();
-
- /* Error: ECTCNEVERSET */
- if (count <= 1)
- goto bad_ctc;
-
- /* 64-bit subtract - gcc just messes up with long longs */
- __asm__("subl %2,%0\n\t"
- "sbbl %3,%1"
- :"=a" (end.lo), "=d" (end.hi)
- :"g" (start.lo), "g" (start.hi),
- "0" (end.lo), "1" (end.hi));
-
- /* Error: ECPUTOOFAST */
- if (end.hi)
- goto bad_ctc;
-
-
- /* Error: ECPUTOOSLOW */
- if (end.lo <= CALIBRATE_DIVISOR)
- goto bad_ctc;
-
- return (end.lo + CALIBRATE_DIVISOR -1)/CALIBRATE_DIVISOR;
- }
-
- /*
- * The CTC wasn't reliable: we got a hit on the very first read,
- * or the CPU was so fast/slow that the quotient wouldn't fit in
- * 32 bits..
- */
-bad_ctc:
- print_err("bad_ctc\n");
- return 0;
-}
-#endif
-
/* spll_raw_clk = SYSREF * FbDIV,
* GLIU Clock = spll_raw_clk / MDIV
- * CPU Clock = sppl_raw_clk / VDIV
+ * CPU Clock = spll_raw_clk / VDIV
*/
/* table for Feedback divisor to FbDiv register value */
@@ -88,37 +45,17 @@
49, 40, 19, 59, 32, 54, 35, 0, 41, 60, 55, 0, 61, 0, 0, 0
};
-static const unsigned char pci33_ddr_crt [] = {
- /* FbDIV, VDIV, MDIV CPU/GeodeLink */
- 12, 2, 3, // 200/133
- 16, 2, 3, // 266/177
- 18, 2, 3, // 300/200
- 20, 2, 3, // 333/222
- 22, 2, 3, // 366/244
- 24, 2, 3, // 400/266
- 26, 2, 3 // 433/289
-};
+/* FbDIV VDIV MDIV CPU/GeodeLink */
+/* 12 2 3 200/133 */
+/* 16 2 3 266/177 */
+/* 18 2 3 300/200 */
+/* 20 2 3 333/222 */
+/* 22 2 3 366/244 */
+/* 24 2 3 400/266 */
+/* 26 2 3 433/289 */
-#if 0
-static unsigned int get_memory_speed(void)
-{
- unsigned char val, hi, lo;
- val = spd_read_byte(0xA0, 9);
- hi = (val >> 4) & 0x0f;
- lo = val & 0x0f;
-
- return 20000/(hi*10 + lo);
-}
-#endif
-
-#define USE_GOODRICH_VERSION 1
-
-#if USE_GOODRICH_VERSION
-///////////////////////////////////////////////////////////////////////////////
-// Goodrich Version of pll_reset
-
-// PLLCHECK_COMPLETED is the "we've already done this" flag
+/* PLLCHECK_COMPLETED is the "we've already done this" flag */
#define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT)
#ifndef RSTPPL_LOWER_BYPASS_SET
@@ -127,90 +64,104 @@
#define DEFAULT_MDIV 3
#define DEFAULT_VDIV 2
-#define DEFAULT_FBDIV 22 // 366/244 ; 24 400/266 018 ;300/200
static void pll_reset(void)
{
msr_t msrGlcpSysRstpll;
unsigned MDIV_VDIV_FBDIV;
- unsigned SyncBits; // store the sync bits in up ebx
+ unsigned SyncBits; /* store the sync bits in up ebx */
+ unsigned DEFAULT_FBDIV;
- // clear the Bypass bit
+ if (CONFIG_PROCESSOR_MHZ == 400){
+ DEFAULT_FBDIV = 24;
+ }
+ else if (CONFIG_PROCESSOR_MHZ == 366){
+ DEFAULT_FBDIV = 22;
+ }
+ else if (CONFIG_PROCESSOR_MHZ == 300){
+ DEFAULT_FBDIV = 18;
+ } else {
+ printk(BIOS_ERR, "Unsupported PROCESSOR_MHZ setting !\n");
+ post_code(POST_PLL_CPU_VER_FAIL);
+ __asm__ __volatile__("hlt\n");
+ }
- // If the straps say we are in bypass and the syspll is not AND there are no software
- // bits set then FS2 or something set up the PLL and we should not change it.
+ /* clear the Bypass bit */
+ /* If the straps say we are in bypass and the syspll is not AND there are no software */
+ /* bits set then FS2 or something set up the PLL and we should not change it. */
+
msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
msrGlcpSysRstpll.lo &= ~RSTPPL_LOWER_BYPASS_SET;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- // If the "we've already been here" flag is set, don't reconfigure the pll
+ /* If the "we've already been here" flag is set, don't reconfigure the pll */
if ( !(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED ) )
- { // we haven't configured the PLL; do it now
+ { /* we haven't configured the PLL; do it now */
- // Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the
- // correct Strap Table.
+ /* Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the */
+ /* correct Strap Table. */
post_code(POST_PLL_INIT);
- // configure for DDR
+ /* configure for DDR */
msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- // Use Manual settings
- // UseManual:
+ /* Use Manual settings */
+ /* UseManual: */
post_code(POST_PLL_MANUAL);
- // DIV settings manually entered.
- // ax = VDIV, upper eax = MDIV, upper ecx = FbDIV
- // use gs and fs since we don't need them.
+ /* DIV settings manually entered. */
+ /* ax = VDIV, upper eax = MDIV, upper ecx = FbDIV */
+ /* use gs and fs since we don't need them. */
- // ProgramClocks:
- // ax = VDIV, upper eax = MDIV, upper ecx = FbDIV
- // move everything into ebx
- // VDIV
+ /* ProgramClocks: */
+ /* ax = VDIV, upper eax = MDIV, upper ecx = FbDIV */
+ /* move everything into ebx */
+ /* VDIV */
MDIV_VDIV_FBDIV = ((DEFAULT_VDIV - 2) << RSTPLL_UPPER_VDIV_SHIFT);
- // MDIV
+ /* MDIV */
MDIV_VDIV_FBDIV |= ((DEFAULT_MDIV - 2) << RSTPLL_UPPER_MDIV_SHIFT);
- // FbDIV
+ /* FbDIV */
MDIV_VDIV_FBDIV |= (plldiv2fbdiv[DEFAULT_FBDIV] << RSTPLL_UPPER_FBDIV_SHIFT);
- // write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values
+ /* write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values */
msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
msrGlcpSysRstpll.hi = MDIV_VDIV_FBDIV;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- // Set Reset, LockWait, and SW flag
- // DoReset:
+ /* Set Reset, LockWait, and SW flag */
+ /* DoReset: */
- // CheckSemiSync proc
- // Check for Semi-Sync in GeodeLink and CPU.
- // We need to do this here since the strap settings don't account for these bits.
- SyncBits = 0; // store the sync bits in up ebx
+ /* CheckSemiSync proc */
+ /* Check for Semi-Sync in GeodeLink and CPU. */
+ /* We need to do this here since the strap settings don't account for these bits. */
+ SyncBits = 0; /* store the sync bits in up ebx */
- // Check for Bypass mode.
+ /* Check for Bypass mode. */
if (msrGlcpSysRstpll.lo & RSTPPL_LOWER_BYPASS_SET)
{
- // If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will.
+ /* If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will. */
SyncBits |= RSTPPL_LOWER_CPU_SEMI_SYNC_SET;
}
else
{
- // CheckPCIsync:
- // If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater
- // look up the real divider... if we get a 0 we have serious problems
+ /* CheckPCIsync: */
+ /* If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater */
+ /* look up the real divider... if we get a 0 we have serious problems */
if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] %
(((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)) )
{
SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET;
}
- // CheckCPUSync:
- // If Vdiv/Mdiv is evenly divisible then set the CPU semi-sync.
- // CPU is always greater or equal.
+ /* CheckCPUSync: */
+ /* If Vdiv/Mdiv is evenly divisible then set the CPU semi-sync. */
+ /* CPU is always greater or equal. */
if (!((((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x07) + 2) %
(((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_VDIV_SHIFT) & 0x0F) + 2)))
{
@@ -219,103 +170,35 @@
}
- // SetSync:
+ /* SetSync: */
msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_PCI_SEMI_SYNC_SET | RSTPPL_LOWER_CPU_SEMI_SYNC_SET);
msrGlcpSysRstpll.lo |= SyncBits;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- // CheckSemiSync endp
+ /* CheckSemiSync endp */
- // now we do the reset
- // Set hold count to 99 (063h)
+ /* now we do the reset */
+ /* Set hold count to 99 (063h) */
msrGlcpSysRstpll.lo &= ~(0x0FF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
msrGlcpSysRstpll.lo |= (0x0DE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
msrGlcpSysRstpll.lo |= PLLCHECK_COMPLETED; // Say we are done
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- // Don't want to use LOCKWAIT
+ /* Don't want to use LOCKWAIT */
msrGlcpSysRstpll.lo |= (RSTPPL_LOWER_PLL_RESET_SET + RSTPPL_LOWER_PD_SET);
msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- // You should never get here..... The chip has reset.
+ /* You should never get here..... The chip has reset. */
post_code(POST_PLL_RESET_FAIL);
while (1);
- } // we haven't configured the PLL; do it now
+ } /* we haven't configured the PLL; do it now */
}
-// End of Goodrich version of pll_reset
-///////////////////////////////////////////////////////////////////////////////
-#else // #if USE_GOODRICH_VERSION
-
-static void pll_reset(void)
+static unsigned int GeodeLinkSpeed(void)
{
- msr_t msr;
- unsigned int sysref, spll_raw, cpu_core, gliu;
- unsigned mdiv, vdiv, fbdiv;
-
- /* get CPU core clock in MHZ */
- cpu_core = calibrate_tsc();
- print_debug("Cpu core is ");
- print_debug_hex32(cpu_core);
- print_debug("\n");
-
- msr = rdmsr(GLCP_SYS_RSTPLL);
- if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) {
-#if 0
- print_debug("MSR ");
- print_debug_hex32(GLCP_SYS_RSTPLL);
- print_debug("is ");
- print_debug_hex32(msr.hi);
- print_debug(":");
- print_debug_hex32(msr.lo);
-
- msr.hi = PLLMSRhi;
- msr.lo = PLLMSRlo;
- wrmsr(GLCP_SYS_RSTPLL, msr);
- msr.lo |= PLLMSRlo1;
- wrmsr(GLCP_SYS_RSTPLL, msr);
-
- print_debug("Reset PLL\n");
-
- msr.lo |= PLLMSRlo2;
- wrmsr(GLCP_SYS_RSTPLL,msr);
- print_debug("should not be here\n");
-#endif
- print_err("shit");
- while (1)
- ;
- }
-
- if (msr.lo & GLCP_SYS_RSTPLL_SWFLAGS_MASK) {
- /* PLL is already set and we are reboot from PLL reset */
- print_debug("reboot from BIOS reset\n");
- return;
- }
-
- /* get the sysref clock rate */
- vdiv = (msr.hi >> GLCP_SYS_RSTPLL_VDIV_SHIFT) & 0x07;
- vdiv += 2;
- fbdiv = (msr.hi >> GLCP_SYS_RSTPLL_FBDIV_SHIFT) & 0x3f;
- fbdiv = fbdiv2plldiv[fbdiv];
- spll_raw = cpu_core * vdiv;
- sysref = spll_raw / fbdiv;
-
- /* get target memory rate by SPD */
- //gliu = get_memory_speed();
-
- msr.hi = 0x00000019;
- msr.lo = 0x06de0378;
- wrmsr(0x4c000014, msr);
- msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24));
- wrmsr(0x4c000014, msr);
-
- print_debug("Reset PLL\n");
-
- msr.lo |= ((1<<14) |(1<<13) | (1<<0));
- wrmsr(0x4c000014,msr);
-
- print_debug("should not be here\n");
+ unsigned geodelinkspeed;
+ geodelinkspeed = ((CONFIG_PROCESSOR_MHZ * DEFAULT_VDIV) / DEFAULT_MDIV);
+ return (geodelinkspeed);
}
-#endif // #if USE_GOODRICH_VERSION
This patch brings the adapted Geode LX auto DRAM detect code to GX2 , cleans up some files and adds a processor speed setting function in human readable Mhz. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> It is Abuild and boot tested on my Wyse S50 with 3 different SODIMMs (128Mb pc2700, 256Mb pc2100, 512Mb pc2700) and each dimm with all three speed settings. (my S50 runs linux under as well as overclocked at 400Mhz!) Thanks to Jens Rottmann for providing the memory chip types for the Lippert Frontrunner. Thanks, Nils.