Patchwork Remove various .c #includes from Intel 440BX/82371EB boards

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Submitter Uwe Hermann
Date 2010-10-07 21:50:14
Message ID <20101007215014.GO3256@greenwood>
Download mbox | patch
Permalink /patch/2072/
State New
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Comments

Uwe Hermann - 2010-10-07 21:50:14
See patch.

This works fine (tested in abuild) for all 440BX boards, but it seems to
break the build of the QEMU target.

I tried to fix it but I don't really know how it can be done. The
problem is (I guess) that the QEMU target is still using ROMCC and
all other 82371EB boards don't (?) Any ideas?

    CC         southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o
    GEN        romstage/ldscript.ld
    LINK       coreboot.romstage
build/southbridge/intel/i82371eb/i82371eb_early_pm.romstage.o: In function `enable_pm':
/home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_pm.c:42: undefined reference to `die'
build/southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o: In function `enable_smbus':
/home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c:47: undefined reference to `die'
collect2: ld returned 1 exit status
make: *** [build/coreboot.romstage] Error 1


Uwe.
Corey Osgood - 2010-10-08 06:41:40
On Thu, Oct 7, 2010 at 5:50 PM, Uwe Hermann <uwe@hermann-uwe.de> wrote:
> See patch.
>
> This works fine (tested in abuild) for all 440BX boards, but it seems to
> break the build of the QEMU target.
>
> I tried to fix it but I don't really know how it can be done. The
> problem is (I guess) that the QEMU target is still using ROMCC and
> all other 82371EB boards don't (?) Any ideas?
>
>    CC         southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o
>    GEN        romstage/ldscript.ld
>    LINK       coreboot.romstage
> build/southbridge/intel/i82371eb/i82371eb_early_pm.romstage.o: In function `enable_pm':
> /home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_pm.c:42: undefined reference to `die'
> build/southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o: In function `enable_smbus':
> /home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c:47: undefined reference to `die'
> collect2: ld returned 1 exit status
> make: *** [build/coreboot.romstage] Error 1
>

I think I've found the problem, include/console/console.h:

62 #ifndef __ROMCC__
63 void console_init(void);
64 void post_code(u8 value);
65 void __attribute__ ((noreturn)) die(const char *msg);

Maybe move that definition a few lines up, and see what happens? Or
else converting the QEMU target to CAR seems like the other option.

-Corey



>
> Uwe.
> --
> http://hermann-uwe.de     | http://sigrok.org
> http://randomprojects.org | http://unmaintained-free-software.org
>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
Warren Turkal - 2010-10-08 09:28:53
Any reason not to convert QEMU to car?

Thanks,
wt

On Thu, Oct 7, 2010 at 11:41 PM, Corey Osgood <corey.osgood@gmail.com> wrote:
> On Thu, Oct 7, 2010 at 5:50 PM, Uwe Hermann <uwe@hermann-uwe.de> wrote:
>> See patch.
>>
>> This works fine (tested in abuild) for all 440BX boards, but it seems to
>> break the build of the QEMU target.
>>
>> I tried to fix it but I don't really know how it can be done. The
>> problem is (I guess) that the QEMU target is still using ROMCC and
>> all other 82371EB boards don't (?) Any ideas?
>>
>>    CC         southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o
>>    GEN        romstage/ldscript.ld
>>    LINK       coreboot.romstage
>> build/southbridge/intel/i82371eb/i82371eb_early_pm.romstage.o: In function `enable_pm':
>> /home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_pm.c:42: undefined reference to `die'
>> build/southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o: In function `enable_smbus':
>> /home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c:47: undefined reference to `die'
>> collect2: ld returned 1 exit status
>> make: *** [build/coreboot.romstage] Error 1
>>
>
> I think I've found the problem, include/console/console.h:
>
> 62 #ifndef __ROMCC__
> 63 void console_init(void);
> 64 void post_code(u8 value);
> 65 void __attribute__ ((noreturn)) die(const char *msg);
>
> Maybe move that definition a few lines up, and see what happens? Or
> else converting the QEMU target to CAR seems like the other option.
>
> -Corey
>
>
>
>>
>> Uwe.
>> --
>> http://hermann-uwe.de     | http://sigrok.org
>> http://randomprojects.org | http://unmaintained-free-software.org
>>
>> --
>> coreboot mailing list: coreboot@coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>

Patch

Remove various .c #includes from Intel 440BX/82371EB boards.

 - Use 'romstage-y' to turn i82371eb_early_pm.c and i82371eb_early_smbus.c
   into distinct compilation units, and don't #include the files anymore
   in romstage.c files.

 - Ditto for lib/debug.c, northbridge/intel/i440bx/raminit.c, and
   northbridge/intel/i440bx/debug.c.

 - Add various header files which are now needed.

 - Make functions that need to be visible non-static.

 - Drop a remaining "select ROMCC" from a 4440BX board.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>

Index: src/southbridge/intel/i82371eb/Makefile.inc
===================================================================
--- src/southbridge/intel/i82371eb/Makefile.inc	(Revision 5919)
+++ src/southbridge/intel/i82371eb/Makefile.inc	(Arbeitskopie)
@@ -25,4 +25,6 @@ 
 driver-y +=  i82371eb_smbus.c
 driver-y +=  i82371eb_reset.c
 
-#romstage-y += i82371eb_early_rom.c
+romstage-y += i82371eb_early_pm.c
+romstage-y += i82371eb_early_smbus.c
+
Index: src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_early_smbus.c	(Revision 5919)
+++ src/southbridge/intel/i82371eb/i82371eb_early_smbus.c	(Arbeitskopie)
@@ -21,13 +21,19 @@ 
 /* TODO: Implement smbus_write_byte(), smbus_recv_byte(), smbus_send_byte(). */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
 #include <device/pci_ids.h>
+#include <device/pci_def.h>
 #include "i82371eb.h"
 #include "i82371eb_smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00
 
-static void enable_smbus(void)
+int smbus_read_byte(u8 device, u8 address);
+
+void enable_smbus(void)
 {
 	device_t dev;
 	u8 reg8;
@@ -57,7 +63,7 @@ 
 	outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS);
 }
 
-static int smbus_read_byte(u8 device, u8 address)
+int smbus_read_byte(u8 device, u8 address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
Index: src/southbridge/intel/i82371eb/i82371eb.h
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb.h	(Revision 5919)
+++ src/southbridge/intel/i82371eb/i82371eb.h	(Arbeitskopie)
@@ -21,11 +21,18 @@ 
 #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 
+#if !defined(ASSEMBLY)
 #if !defined(__PRE_RAM__)
+
+#include <arch/io.h>
+#include <device/device.h>
 #include "chip.h"
+
 void i82371eb_enable(device_t dev);
 void i82371eb_hard_reset(void);
+
 #endif
+#endif
 
 /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
  * 'reg' variable, otherwise it clears those bits.
@@ -55,6 +62,8 @@ 
 #define PMBA		0x40	/* Power management base address */
 #define PMREGMISC	0x80	/* Miscellaneous power management */
 
+#define PM_IO_BASE	0xe400
+
 /* Bit definitions */
 #define EXT_BIOS_ENABLE_1MB	(1 << 9)  /* 1-Meg Extended BIOS Enable */
 #define EXT_BIOS_ENABLE		(1 << 7)  /* Extended BIOS Enable */
Index: src/southbridge/intel/i82371eb/i82371eb_smbus.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_smbus.c	(Revision 5919)
+++ src/southbridge/intel/i82371eb/i82371eb_smbus.c	(Arbeitskopie)
@@ -24,6 +24,7 @@ 
 #include <device/pci_ids.h>
 #include <device/smbus.h>
 #include "i82371eb.h"
+#include "i82371eb_smbus.h"
 
 /* TODO: Needed later? */
 static const struct smbus_bus_operations lops_smbus_bus = {
Index: src/southbridge/intel/i82371eb/i82371eb_smbus.h
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_smbus.h	(Revision 5919)
+++ src/southbridge/intel/i82371eb/i82371eb_smbus.h	(Arbeitskopie)
@@ -10,6 +10,9 @@ 
 #define SMBUS_STATUS_MASK 0x1e
 #define SMBUS_ERROR_FLAG (1<<2)
 
+void enable_smbus(void);
+int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address);
+
 static inline void smbus_delay(void)
 {
 	outb(0x80, 0x80);
@@ -63,7 +66,7 @@ 
 	return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
 }
 
-static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
 {
 	unsigned status_register;
 	unsigned byte;
Index: src/southbridge/intel/i82371eb/i82371eb_early_pm.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_early_pm.c	(Revision 5919)
+++ src/southbridge/intel/i82371eb/i82371eb_early_pm.c	(Arbeitskopie)
@@ -19,12 +19,16 @@ 
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
 #include <device/pci_ids.h>
+#include <console/console.h>
 #include "i82371eb.h"
 
-#define PM_IO_BASE 0xe400
+void enable_pm(void);
 
-static void enable_pm(void)
+void enable_pm(void)
 {
 	device_t dev;
 	u8 reg8;
Index: src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
===================================================================
--- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	(Revision 5919)
+++ src/mainboard/soyo/sy-6ba-plus-iii/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -38,14 +37,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Index: src/mainboard/a-trend/atc-6240/romstage.c
===================================================================
--- src/mainboard/a-trend/atc-6240/romstage.c	(Revision 5919)
+++ src/mainboard/a-trend/atc-6240/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Index: src/mainboard/a-trend/atc-6220/romstage.c
===================================================================
--- src/mainboard/a-trend/atc-6220/romstage.c	(Revision 5919)
+++ src/mainboard/a-trend/atc-6220/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Index: src/mainboard/gigabyte/ga-6bxc/romstage.c
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/romstage.c	(Revision 5919)
+++ src/mainboard/gigabyte/ga-6bxc/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -38,14 +37,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Index: src/mainboard/gigabyte/ga-6bxe/romstage.c
===================================================================
--- src/mainboard/gigabyte/ga-6bxe/romstage.c	(Revision 5919)
+++ src/mainboard/gigabyte/ga-6bxe/romstage.c	(Arbeitskopie)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
@@ -38,14 +38,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	it8671f_48mhz_clkin();
Index: src/mainboard/nokia/ip530/Kconfig
===================================================================
--- src/mainboard/nokia/ip530/Kconfig	(Revision 5919)
+++ src/mainboard/nokia/ip530/Kconfig	(Arbeitskopie)
@@ -28,7 +28,6 @@ 
 	select SOUTHBRIDGE_TI_PCI1X2X
 	select DRIVERS_DEC_21143
 	select BOARD_ROMSIZE_KB_256
-	select ROMCC
 	select PIRQ_ROUTE
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
Index: src/mainboard/nokia/ip530/romstage.c
===================================================================
--- src/mainboard/nokia/ip530/romstage.c	(Revision 5919)
+++ src/mainboard/nokia/ip530/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Index: src/mainboard/biostar/m6tba/romstage.c
===================================================================
--- src/mainboard/biostar/m6tba/romstage.c	(Revision 5919)
+++ src/mainboard/biostar/m6tba/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Index: src/mainboard/azza/pt-6ibd/romstage.c
===================================================================
--- src/mainboard/azza/pt-6ibd/romstage.c	(Revision 5919)
+++ src/mainboard/azza/pt-6ibd/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -39,14 +38,14 @@ 
 /* FIXME: It's a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	/* FIXME: It's a Winbond W83977EF, actually. */
Index: src/mainboard/tyan/s1846/romstage.c
===================================================================
--- src/mainboard/tyan/s1846/romstage.c	(Revision 5919)
+++ src/mainboard/tyan/s1846/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	pc87309_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Index: src/mainboard/abit/be6-ii_v2_0/romstage.c
===================================================================
--- src/mainboard/abit/be6-ii_v2_0/romstage.c	(Revision 5919)
+++ src/mainboard/abit/be6-ii_v2_0/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -39,14 +38,14 @@ 
 /* FIXME: It's a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	/* FIXME: It's a Winbond W83977EF, actually. */
Index: src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
===================================================================
--- src/mainboard/compaq/deskpro_en_sff_p600/romstage.c	(Revision 5919)
+++ src/mainboard/compaq/deskpro_en_sff_p600/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -39,14 +38,14 @@ 
 /* FIXME: This should be PC97307 (but it's buggy at the moment)! */
 #define SERIAL_DEV PNP_DEV(0x15c, PC97317_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	/* FIXME: Should be PC97307! */
Index: src/mainboard/msi/ms6119/romstage.c
===================================================================
--- src/mainboard/msi/ms6119/romstage.c	(Revision 5919)
+++ src/mainboard/msi/ms6119/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Index: src/mainboard/msi/ms6147/romstage.c
===================================================================
--- src/mainboard/msi/ms6147/romstage.c	(Revision 5919)
+++ src/mainboard/msi/ms6147/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include <cpu/x86/bist.h>
@@ -37,14 +36,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Index: src/mainboard/msi/ms6156/romstage.c
===================================================================
--- src/mainboard/msi/ms6156/romstage.c	(Revision 5919)
+++ src/mainboard/msi/ms6156/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Index: src/mainboard/asus/p2b-ls/romstage.c
===================================================================
--- src/mainboard/asus/p2b-ls/romstage.c	(Revision 5919)
+++ src/mainboard/asus/p2b-ls/romstage.c	(Arbeitskopie)
@@ -26,7 +26,7 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
@@ -38,14 +38,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
Index: src/mainboard/asus/p2b/romstage.c
===================================================================
--- src/mainboard/asus/p2b/romstage.c	(Revision 5919)
+++ src/mainboard/asus/p2b/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,14 +36,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Index: src/mainboard/asus/p2b-d/romstage.c
===================================================================
--- src/mainboard/asus/p2b-d/romstage.c	(Revision 5919)
+++ src/mainboard/asus/p2b-d/romstage.c	(Arbeitskopie)
@@ -27,7 +27,7 @@ 
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
@@ -38,14 +38,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	enable_lapic();		/* FIXME? */
Index: src/mainboard/asus/p2b-f/romstage.c
===================================================================
--- src/mainboard/asus/p2b-f/romstage.c	(Revision 5919)
+++ src/mainboard/asus/p2b-f/romstage.c	(Arbeitskopie)
@@ -26,9 +26,8 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -39,14 +38,14 @@ 
 /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	/* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
Index: src/mainboard/asus/p2b-ds/romstage.c
===================================================================
--- src/mainboard/asus/p2b-ds/romstage.c	(Revision 5919)
+++ src/mainboard/asus/p2b-ds/romstage.c	(Arbeitskopie)
@@ -27,9 +27,8 @@ 
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -38,14 +37,14 @@ 
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 void main(unsigned long bist)
 {
 	enable_lapic();		/* FIXME? */
Index: src/mainboard/asus/p3b-f/romstage.c
===================================================================
--- src/mainboard/asus/p3b-f/romstage.c	(Revision 5919)
+++ src/mainboard/asus/p3b-f/romstage.c	(Arbeitskopie)
@@ -26,10 +26,8 @@ 
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
-#include "southbridge/intel/i82371eb/i82371eb_early_pm.c"
+#include "southbridge/intel/i82371eb/i82371eb.h"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
@@ -37,17 +35,18 @@ 
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
 #include <lib.h>
 
+void enable_pm(void);
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
 /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
+int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i440bx/raminit.c"
-#include "northbridge/intel/i440bx/debug.c"
-
 /*
  * ASUS P3B-F specific SPD enable magic.
  *
Index: src/northbridge/intel/i440bx/raminit.c
===================================================================
--- src/northbridge/intel/i440bx/raminit.c	(Revision 5919)
+++ src/northbridge/intel/i440bx/raminit.c	(Arbeitskopie)
@@ -21,7 +21,12 @@ 
 
 #include <spd.h>
 #include <delay.h>
+#include <stdint.h>
 #include <stdlib.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <console/console.h>
 #include "i440bx.h"
 #include "raminit.h"
 
@@ -630,7 +635,7 @@ 
 Public interface.
 -----------------------------------------------------------------------------*/
 
-static void sdram_set_registers(void)
+void sdram_set_registers(void)
 {
 	int i, max;
 	uint8_t reg;
@@ -956,7 +961,7 @@ 
 	PRINT_DEBUG("\n");
 }
 
-static void sdram_set_spd_registers(void)
+void sdram_set_spd_registers(void)
 {
 	/* Setup DRAM row boundary registers and other attributes. */
 	set_dram_row_attributes();
@@ -972,7 +977,7 @@ 
 	pci_write_config8(NB, DRAMT, 0x03);
 }
 
-static void sdram_enable(void)
+void sdram_enable(void)
 {
 	int i;
 
Index: src/northbridge/intel/i440bx/Makefile.inc
===================================================================
--- src/northbridge/intel/i440bx/Makefile.inc	(Revision 5919)
+++ src/northbridge/intel/i440bx/Makefile.inc	(Arbeitskopie)
@@ -20,3 +20,6 @@ 
 
 driver-y += northbridge.c
 
+romstage-y += raminit.c
+romstage-y += debug.c
+
Index: src/northbridge/intel/i440bx/debug.c
===================================================================
--- src/northbridge/intel/i440bx/debug.c	(Revision 5919)
+++ src/northbridge/intel/i440bx/debug.c	(Arbeitskopie)
@@ -1,4 +1,6 @@ 
-static void dump_spd_registers(void)
+#include "raminit.h"
+
+void dump_spd_registers(void)
 {
 #if CONFIG_DEBUG_RAM_SETUP
 	int i;
Index: src/northbridge/intel/i440bx/raminit.h
===================================================================
--- src/northbridge/intel/i440bx/raminit.h	(Revision 5919)
+++ src/northbridge/intel/i440bx/raminit.h	(Arbeitskopie)
@@ -26,5 +26,12 @@ 
 
 /* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */
 #define DIMM_SPD_BASE	0x50
+ 
+/* Function prototypes. */
+int spd_read_byte(unsigned int device, unsigned int address);
+void sdram_set_registers(void);
+void sdram_set_spd_registers(void);
+void sdram_enable(void);
+void dump_spd_registers(void);
 
 #endif				/* RAMINIT_H */