Patchwork fix dst-link field in RS780/RS690 function ProgK8TempMmioBase

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Submitter Liu Tao
Date 2010-10-11 03:23:37
Message ID <AANLkTi=ouGLsRZCSAjmTD5fqN+A_izxwvLN3OLnWgJJx@mail.gmail.com>
Download mbox | patch
Permalink /patch/2089/
State New
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Comments

Liu Tao - 2010-10-11 03:23:37
Hello,

in RS780/RS690 ProgK8TempMmioBase() function, the dst-link field is set to zero,
so for boards with RS780 not on CPU's HT chain 0, the function will
mis-configure
the MMIO dst-link routing, and the following enable_pcie_bar3()
function will hang
when it visits the MMIO.

the following patch fixes the problem, and tested on a K8 board with RS780 on HT
chain 1.

Signed-off-by: Liu Tao <liutao1980@gmail.com>
Warren Turkal - 2010-10-11 06:00:02
If the rs class boards are similar enough to have the same code, why
not just pull the code into some common location instead of editing
each mainboard?

Thanks,
wt

On Sun, Oct 10, 2010 at 8:23 PM, Liu Tao <liutao1980@gmail.com> wrote:
> Hello,
>
> in RS780/RS690 ProgK8TempMmioBase() function, the dst-link field is set to zero,
> so for boards with RS780 not on CPU's HT chain 0, the function will
> mis-configure
> the MMIO dst-link routing, and the following enable_pcie_bar3()
> function will hang
> when it visits the MMIO.
>
> the following patch fixes the problem, and tested on a K8 board with RS780 on HT
> chain 1.
>
> Signed-off-by: Liu Tao <liutao1980@gmail.com>
>
> --
> Regards,
> Liu Tao
>
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
Uwe Hermann - 2010-10-17 21:59:26
On Mon, Oct 11, 2010 at 11:23:37AM +0800, Liu Tao wrote:
> Hello,
> 
> in RS780/RS690 ProgK8TempMmioBase() function, the dst-link field is set to zero,
> so for boards with RS780 not on CPU's HT chain 0, the function will
> mis-configure
> the MMIO dst-link routing, and the following enable_pcie_bar3()
> function will hang
> when it visits the MMIO.
> 
> the following patch fixes the problem, and tested on a K8 board with RS780 on HT
> chain 1.
> 
> Signed-off-by: Liu Tao <liutao1980@gmail.com>

Thanks, r5959.


Uwe.

Patch

Index: src/southbridge/amd/rs780/rs780_cmn.c
===================================================================
--- src/southbridge/amd/rs780/rs780_cmn.c	(revision 5923)
+++ src/southbridge/amd/rs780/rs780_cmn.c	(working copy)
@@ -200,15 +200,23 @@ 
 {
 	/* K8 Function1 is address map */
 	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
 
 	if (in_out) {
+		u32 dword, sblk;
+
+		/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
+		dword = pci_read_config32(k8_f0, 0x64);
+		sblk = (dword >> 8) & 0x3;
+
+		/* fill MMIO limit/base pair */
 		pci_write_config32(k8_f1, 0xbc,
 				   (((pcie_base_add + 0x10000000 -
-				     1) >> 8) & 0xffffff00) | 0x80);
+				     1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
 		pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
 		pci_write_config32(k8_f1, 0xb4,
-				   ((mmio_base_add + 0x10000000 -
-				     1) >> 8) & 0xffffff00);
+				   (((mmio_base_add + 0x10000000 -
+				     1) >> 8) & 0xffffff00) | (sblk << 4));
 		pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
 	} else {
 		pci_write_config32(k8_f1, 0xb8, 0);
Index: src/southbridge/amd/rs690/rs690_cmn.c
===================================================================
--- src/southbridge/amd/rs690/rs690_cmn.c	(revision 5923)
+++ src/southbridge/amd/rs690/rs690_cmn.c	(working copy)
@@ -202,15 +202,23 @@ 
 {
 	/* K8 Function1 is address map */
 	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
 
 	if (in_out) {
+		u32 dword, sblk;
+
+		/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
+		dword = pci_read_config32(k8_f0, 0x64);
+		sblk = (dword >> 8) & 0x3;
+
+		/* fill MMIO limit/base pair */
 		pci_write_config32(k8_f1, 0xbc,
 				   (((pcie_base_add + 0x10000000 -
-				     1) >> 8) & 0xffffff00) | 0x80);
+				     1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
 		pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
 		pci_write_config32(k8_f1, 0xb4,
-				   ((mmio_base_add + 0x10000000 -
-				     1) >> 8) & 0xffffff00);
+				   (((mmio_base_add + 0x10000000 -
+				     1) >> 8) & 0xffffff00) | (sblk << 4));
 		pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
 	} else {
 		pci_write_config32(k8_f1, 0xb8, 0);