| Submitter | Uwe Hermann |
|---|---|
| Date | 2010-10-14 23:02:34 |
| Message ID | <20101014230234.GF3256@greenwood> |
| Download | mbox | patch |
| Permalink | /patch/2110/ |
| State | Accepted |
| Headers | show |
Comments
Uwe Hermann wrote: > Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. > > This CAR implementation hardcodes the Cache-as-RAM base address to: > > 0xd0000 - CacheSize > > so the DCACHE_RAM_BASE is never actually used for this implementation > and these sockets. > > Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se>
I see that this removes the DCACHE_RAM_BASE from the src/cpu/intel hierarchy, but there are also intel mainboards that define this value, apparently needlessly. Should this patch include those also? Thanks, wt On Thursday, October 14, 2010 04:02:34 pm Uwe Hermann wrote: > See patch. > > > Uwe.
Patch
Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. This CAR implementation hardcodes the Cache-as-RAM base address to: 0xd0000 - CacheSize so the DCACHE_RAM_BASE is never actually used for this implementation and these sockets. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Index: src/cpu/intel/socket_PGA370/Kconfig =================================================================== --- src/cpu/intel/socket_PGA370/Kconfig (Revision 5951) +++ src/cpu/intel/socket_PGA370/Kconfig (Arbeitskopie) @@ -30,10 +30,6 @@ bool default n -config DCACHE_RAM_BASE - hex - default 0xc0000 - config DCACHE_RAM_SIZE hex default 0x01000 Index: src/cpu/intel/socket_FC_PGA370/Kconfig =================================================================== --- src/cpu/intel/socket_FC_PGA370/Kconfig (Revision 5951) +++ src/cpu/intel/socket_FC_PGA370/Kconfig (Arbeitskopie) @@ -26,11 +26,6 @@ select CACHE_AS_RAM select TINY_BOOTBLOCK -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - depends on CPU_INTEL_SOCKET_FC_PGA370 - config DCACHE_RAM_SIZE hex default 0x8000 Index: src/cpu/intel/slot_1/Kconfig =================================================================== --- src/cpu/intel/slot_1/Kconfig (Revision 5951) +++ src/cpu/intel/slot_1/Kconfig (Arbeitskopie) @@ -21,11 +21,6 @@ bool select CACHE_AS_RAM -config DCACHE_RAM_BASE - hex - default 0xc0000 - depends on CPU_INTEL_SLOT_1 - config DCACHE_RAM_SIZE hex default 0x01000 Index: src/cpu/intel/slot_2/Kconfig =================================================================== --- src/cpu/intel/slot_2/Kconfig (Revision 5951) +++ src/cpu/intel/slot_2/Kconfig (Arbeitskopie) @@ -20,11 +20,6 @@ config CPU_INTEL_SLOT_2 bool -config DCACHE_RAM_BASE - hex - default 0xc0000 - depends on CPU_INTEL_SLOT_2 - config DCACHE_RAM_SIZE hex default 0x01000