From patchwork Sun Oct 17 00:48:15 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: model_65x CPU support Date: Sun, 17 Oct 2010 00:48:15 -0000 From: Keith Hui X-Patchwork-Id: 2126 Message-Id: To: coreboot@coreboot.org >Keith Hui wrote: >> Attached patch moves support for Deschutes Slot 1 CPUs (model_65x) >> into its own home. >Then I guess the patch should also delete some lines in existing files? Yes. I knew I must be missing something. (Oops) See attached patch. Signed-off-by: Keith Hui >> This is similar to the Katmai patch I submitted before, but without >> microcode this time. With 17 of them they will make the patch too >> large. I think I'll defer them for later or someone else*, hehe. :D >> >> abuild-tested. > >It doesn't look like the new code is used anywhere? Should it be? It should be used from cpu/intel/slot_1. >> * also because I like to keep all microcodes for the same family >> within one file instead of one microcode per file. >We want microcode updates to be as close as possible to upstream How upstream are we talking about? :P These updates come from Intel as one big .h file. ;-) >format. Eventually I think we want to put them verbatim into cbfs. This I agree wholeheartedly. Did I ever mention that Award also stuff their microcode updates this way into the firmware image? And hey, I might as well take a crack at this! But a bit of scheduling headache then awaits. How much CPU init do we need to do before we start drawing things in from the cbfs? Is there anything that cannot be done until microcode updates are loaded? Is cpu_dev_ops.init() an appropriate place to access cbfs? If not, from where? Cheers Keith Removes model_65x CPUIDs from model_6xx code. They now have their own home at cpu/intel/model_65x. Signed-off-by: Keith Hui Index: src/cpu/intel/model_6xx/model_6xx_init.c =================================================================== --- src/cpu/intel/model_6xx/model_6xx_init.c (revision 5953) +++ src/cpu/intel/model_6xx/model_6xx_init.c (working copy) @@ -84,11 +84,6 @@ { X86_VENDOR_INTEL, 0x0633 }, /* PII, C0 */ { X86_VENDOR_INTEL, 0x0634 }, /* PII, C1 */ - { X86_VENDOR_INTEL, 0x0650 }, /* PII/Celeron, dA0/mdA0/A0 */ - { X86_VENDOR_INTEL, 0x0651 }, /* PII/Celeron, dA1/A1 */ - { X86_VENDOR_INTEL, 0x0652 }, /* PII/Celeron/Xeon, dB0/mdB0/B0 */ - { X86_VENDOR_INTEL, 0x0653 }, /* PII/Xeon, dB1/B1 */ - { X86_VENDOR_INTEL, 0x0660 }, /* Celeron, A0 */ { X86_VENDOR_INTEL, 0x0665 }, /* Celeron, B0 */ { X86_VENDOR_INTEL, 0x066a }, /* PII, mdxA0/dmmA0 + others */