Patchwork Extension to inteltool and a request

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Submitter Keith Hui
Date 2010-10-20 04:57:21
Message ID <AANLkTimCnR9RdDSMpNYk72DrP6rHvemX41R-f3ZZVCVk@mail.gmail.com>
Download mbox | patch
Permalink /patch/2149/
State New
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Comments

Keith Hui - 2010-10-20 04:57:21
Hi all,

This patch extends inteltool's MSR dumping to all Slot 1 Intel CPUs.

I made this an attempt to gather some information for an updated L2
patch, so I have a request to all,

Can anyone with a Slot 1 CPU apply the attached patch, compile
inteltool, and post the output together with some information on your
CPU?

Thanks.

Patch is Signed-off-by: Keith Hui <buurin@gmail.com>
if it's useful for the future and worth committing.
Svante Signell - 2010-10-20 08:58:51
On Wed, 2010-10-20 at 00:57 -0400, Keith Hui wrote:
> Hi all,
> 
> This patch extends inteltool's MSR dumping to all Slot 1 Intel CPUs.
> 
> I made this an attempt to gather some information for an updated L2
> patch, so I have a request to all,
> 
> Can anyone with a Slot 1 CPU apply the attached patch, compile
> inteltool, and post the output together with some information on your
> CPU?
> Thanks.

Attached info for an MS-6120 Celeron dual-slot1-cpu 300MHz@450MHz from a lurker.

> Patch is Signed-off-by: Keith Hui <buurin@gmail.com>
> if it's useful for the future and worth committing.
Intel CPU: Processor Type: 0, Family 6, Model 6, Stepping 5
Intel Northbridge: 8086:7190 (82443BX)
Intel Southbridge: 8086:7110 (82371AB/EB/MB)

============= GPIOS =============

This southbridge has GPIOs in the PM unit.



============= RCBA ==============

Error: Dumping RCBA on this southbridge is not (yet) supported.



============= PMBASE ============

PMBASE = 0x0000 (IO)

pmbase+0x0000: 0x0000     (PMSTS)
pmbase+0x0002: 0x0000     (PMEN)
pmbase+0x0004: 0x0000     (PMCNTRL)
pmbase+0x0006: 0x0000     (RESERVED)
pmbase+0x0008: 0x00       (PMTMR)
pmbase+0x0009: 0xff       (RESERVED)
pmbase+0x000a: 0xff       (RESERVED)
pmbase+0x000b: 0xff       (RESERVED)
pmbase+0x000c: 0xffff     (GPSTS)
pmbase+0x000e: 0xffff     (GPEN)
pmbase+0x0010: 0x00000000 (PCNTRL)
pmbase+0x0018: 0x0000     (GLBSTS)
pmbase+0x001a: 0xffff     (RESERVED)
pmbase+0x001c: 0xffffffff (DEVSTS)
pmbase+0x0020: 0x3939     (GLBEN)
pmbase+0x0022: 0xff       (RESERVED)
pmbase+0x0023: 0xff       (RESERVED)
pmbase+0x0024: 0x39       (RESERVED)
pmbase+0x0025: 0xff       (RESERVED)
pmbase+0x0026: 0xff       (RESERVED)
pmbase+0x0027: 0xff       (RESERVED)
pmbase+0x0028: 0x39393939 (GLBCTL)
pmbase+0x002c: 0x39393939 (DEVCTL)
pmbase+0x0030: 0x39       (GPIREG 0)
pmbase+0x0031: 0xff       (GPIREG 1)
pmbase+0x0032: 0xff       (GPIREG 2)
pmbase+0x0033: 0xff       (GPIREG 3)
pmbase+0x0034: 0x39       (GPOREG 0)
pmbase+0x0035: 0xff       (GPOREG 1)
pmbase+0x0036: 0xff       (GPOREG 2)
pmbase+0x0037: 0xff       (GPOREG 3)



============= MCHBAR ============

This northbrigde does not have MCHBAR.



============= EPBAR =============

Error: Dumping EPBAR on this northbridge is not (yet) supported.



============= DMIBAR ============

Error: Dumping DMIBAR on this northbridge is not (yet) supported.


========= PCIEXBAR ========

Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.



===================== SHARED MSRs (All Cores) =====================
 MSR 0x00000010 = 0x000885AB:0x96DE3F5D (IA32_TIME_STAMP_COUNTER)
 MSR 0x00000017 = 0x5CB00000:0x00000000 (IA32_PLATFORM_ID)
 MSR 0x0000001B = 0x00000000:0xFEE00900 (IA32_APIC_BASE)
 MSR 0x0000002A = 0x00000000:0xC5900000 (EBL_CR_POWERON)
 MSR 0x00000033 = 0x00000000:0x00000000 (TEST_CTL)
 (*) MSR 0x0000003F = 0xFFFFFFFF:0xFFFFFFFF (THERM_DIODE_OFFSET)
 MSR 0x0000008B = 0x00000003:0x00000000 (IA32_BIOS_SIGN_ID)
 MSR 0x000000C1 = 0x00088500:0x00000000 (PERFCTR0)
 MSR 0x000000C2 = 0x00088500:0x00000000 (PERFCTR1)
 MSR 0x00000119 = 0x00000000:0x00000003 (BBL_CR_CTL)
 MSR 0x0000011E = 0x00000000:0x0134052B (BBL_CR_CTL3)
 MSR 0x00000179 = 0x00000000:0x00000005 (IA32_MCG_CAP)
 MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS)
 (*) MSR 0x00000198 = 0xFFFFFFFF:0xFFFFFFFF (IA32_PERF_STATUS)
 (*) MSR 0x00000199 = 0xFFFFFFFF:0xFFFFFFFF (IA32_PERF_CONTROL)
 (*) MSR 0x0000019A = 0xFFFFFFFF:0xFFFFFFFF (IA32_CLOCK_MODULATION)
 (*) MSR 0x000001A0 = 0xFFFFFFFF:0xFFFFFFFF (IA32_MISC_ENABLES)
 MSR 0x000001D9 = 0x00000000:0x00000001 (IA32_DEBUGCTL)
 MSR 0x00000200 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE0)
 MSR 0x00000201 = 0x0000000F:0xE0000800 (IA32_MTRR_PHYSMASK0)
 MSR 0x00000202 = 0x00000000:0x20000006 (IA32_MTRR_PHYSBASE1)
 MSR 0x00000203 = 0x0000000F:0xF8000800 (IA32_MTRR_PHYSMASK1)
 MSR 0x00000204 = 0x00000000:0xE8000001 (IA32_MTRR_PHYSBASE2)
 MSR 0x00000205 = 0x0000000F:0xFC000800 (IA32_MTRR_PHYSMASK2)
 MSR 0x00000206 = 0x00000000:0xE4000001 (IA32_MTRR_PHYSBASE3)
 MSR 0x00000207 = 0x0000000F:0xFE000800 (IA32_MTRR_PHYSMASK3)
 MSR 0x00000208 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE4)
 MSR 0x00000209 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK4)
 MSR 0x0000020A = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE5)
 MSR 0x0000020B = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK5)
 MSR 0x0000020C = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE6)
 MSR 0x0000020D = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK6)
 MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7)
 MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7)
 MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000)
 MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000)
 MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000)
 MSR 0x00000268 = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_C0000)
 MSR 0x00000269 = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_C8000)
 MSR 0x0000026A = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_D0000)
 MSR 0x0000026B = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_D8000)
 MSR 0x0000026C = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_E0000)
 MSR 0x0000026D = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_E8000)
 MSR 0x0000026E = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_F0000)
 MSR 0x0000026F = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_F8000)
 MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE)
 MSR 0x00000400 = 0x00000000:0xC5900000 (IA32_MC0_CTL)
 MSR 0x00000401 = 0x10000000:0x00000000 (IA32_MC0_STATUS)
 MSR 0x00000402 = 0x00000000:0x00000000 (IA32_MC0_ADDR)
 MSR 0x0000040C = 0x00000000:0x00000001 (IA32_MC4_CTL)
 MSR 0x0000040D = 0x00000000:0x00000000 (IA32_MC4_STATUS)
 (*) MSR 0x0000040E = 0xFFFFFFFF:0xFFFFFFFF (IA32_MC4_ADDR)

(*) Some MSRs could not be read. The marked values are unreliable.
processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 6
model name	: Celeron (Mendocino)
stepping	: 5
cpu MHz		: 451.025
cache size	: 128 KB
fdiv_bug	: no
hlt_bug		: no
f00f_bug	: no
coma_bug	: no
fpu		: yes
fpu_exception	: yes
cpuid level	: 2
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pse36 mmx fxsr
bogomips	: 902.05
clflush size	: 32
cache_alignment	: 32
address sizes	: 36 bits physical, 32 bits virtual
power management:

processor	: 1
vendor_id	: GenuineIntel
cpu family	: 6
model		: 6
model name	: Celeron (Mendocino)
stepping	: 5
cpu MHz		: 451.025
cache size	: 128 KB
fdiv_bug	: no
hlt_bug		: no
f00f_bug	: no
coma_bug	: no
fpu		: yes
fpu_exception	: yes
cpuid level	: 2
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pse36 mmx fxsr
bogomips	: 902.13
clflush size	: 32
cache_alignment	: 32
address sizes	: 36 bits physical, 32 bits virtual
power management:
Andrew Morgan - 2010-10-21 02:01:27
On 20/10/10 05:57, Keith Hui wrote:
> Can anyone with a Slot 1 CPU apply the attached patch, compile
> inteltool, and post the output together with some information on your
> CPU?
Looks good, or at least it produces lots of numbers, I wish I knew what 
they meant. :)
Logs attached, /proc/cpuinfo below. Please note that the CPU MHz and 
cache size are wrong, and there is a flag missing. This is from the 
machine while running coreboot, they are different when running the 
vendor BIOS. I can re-run the tests while running the vendor BIOS if 
this would be useful.

processor    : 0
vendor_id    : GenuineIntel
cpu family    : 6
model        : 7
model name    : Pentium III (Katmai)
stepping    : 3
cpu MHz        : 334.094
cache size    : 32 KB
fdiv_bug    : no
hlt_bug        : no
f00f_bug    : no
coma_bug    : no
fpu        : yes
fpu_exception    : yes
cpuid level    : 2
wp        : yes
flags        : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov 
pse36 mmx fxsr sse up
bogomips    : 668.18
clflush size    : 32
cache_alignment    : 32
address sizes    : 36 bits physical, 32 bits virtual
power management:
Don Waugaman - 2010-10-21 04:07:12
On Oct 19, 2010, at 9:57 PM, Keith Hui wrote:

> Hi all,
>
> This patch extends inteltool's MSR dumping to all Slot 1 Intel CPUs.
>
> I made this an attempt to gather some information for an updated L2
> patch, so I have a request to all,
>
> Can anyone with a Slot 1 CPU apply the attached patch, compile
> inteltool, and post the output together with some information on your
> CPU?

I ran this on my computer, a P2B-L with factory BIOS.

Results are attached below - output of /proc/cpuinfo, the original  
inteltool output from revision 5978, and the output after the patch  
was applied.

Thanks,

Don Waugaman
processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 7
model name	: Pentium III (Katmai)
stepping	: 3
cpu MHz		: 601.424
cache size	: 512 KB
fdiv_bug	: no
hlt_bug		: no
f00f_bug	: no
coma_bug	: no
fpu		: yes
fpu_exception	: yes
cpuid level	: 2
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 mtrr pge mca cmov pse36 mmx fxsr sse up
bogomips	: 1202.84
clflush size	: 32
cache_alignment	: 32
address sizes	: 36 bits physical, 32 bits virtual
power management:
Intel CPU: Processor Type: 0, Family 6, Model 7, Stepping 3
Intel Northbridge: 8086:7190 (82443BX)
Intel Southbridge: 8086:7110 (82371AB/EB/MB)

============= GPIOS =============

This southbridge has GPIOs in the PM unit.



============= RCBA ==============

Error: Dumping RCBA on this southbridge is not (yet) supported.



============= PMBASE ============

PMBASE = 0x0000 (IO)

pmbase+0x0000: 0xdbdb     (PMSTS)
pmbase+0x0002: 0xd3d3     (PMEN)
pmbase+0x0004: 0xe6e6     (PMCNTRL)
pmbase+0x0006: 0x3f3f     (RESERVED)
pmbase+0x0008: 0x00       (PMTMR)
pmbase+0x0009: 0xff       (RESERVED)
pmbase+0x000a: 0xff       (RESERVED)
pmbase+0x000b: 0xff       (RESERVED)
pmbase+0x000c: 0xffff     (GPSTS)
pmbase+0x000e: 0xffff     (GPEN)
pmbase+0x0010: 0xdbdbdbdb (PCNTRL)
pmbase+0x0018: 0x0000     (GLBSTS)
pmbase+0x001a: 0xffff     (RESERVED)
pmbase+0x001c: 0xffffffff (DEVSTS)
pmbase+0x0020: 0x0000     (GLBEN)
pmbase+0x0022: 0xff       (RESERVED)
pmbase+0x0023: 0xff       (RESERVED)
pmbase+0x0024: 0x00       (RESERVED)
pmbase+0x0025: 0x58       (RESERVED)
pmbase+0x0026: 0xff       (RESERVED)
pmbase+0x0027: 0xff       (RESERVED)
pmbase+0x0028: 0x00000000 (GLBCTL)
pmbase+0x002c: 0x00000000 (DEVCTL)
pmbase+0x0030: 0x00       (GPIREG 0)
pmbase+0x0031: 0x58       (GPIREG 1)
pmbase+0x0032: 0xff       (GPIREG 2)
pmbase+0x0033: 0xff       (GPIREG 3)
pmbase+0x0034: 0x00       (GPOREG 0)
pmbase+0x0035: 0x58       (GPOREG 1)
pmbase+0x0036: 0xff       (GPOREG 2)
pmbase+0x0037: 0xff       (GPOREG 3)



============= MCHBAR ============

This northbrigde does not have MCHBAR.



============= EPBAR =============

Error: Dumping EPBAR on this northbridge is not (yet) supported.



============= DMIBAR ============

Error: Dumping DMIBAR on this northbridge is not (yet) supported.


========= PCIEXBAR ========

Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.


Error: Dumping MSRs on this CPU (0x000670) is not (yet) supported.
Intel CPU: Processor Type: 0, Family 6, Model 7, Stepping 3
Intel Northbridge: 8086:7190 (82443BX)
Intel Southbridge: 8086:7110 (82371AB/EB/MB)

============= GPIOS =============

This southbridge has GPIOs in the PM unit.



============= RCBA ==============

Error: Dumping RCBA on this southbridge is not (yet) supported.



============= PMBASE ============

PMBASE = 0x0000 (IO)

pmbase+0x0000: 0xabab     (PMSTS)
pmbase+0x0002: 0xfbfb     (PMEN)
pmbase+0x0004: 0xbaba     (PMCNTRL)
pmbase+0x0006: 0xfefe     (RESERVED)
pmbase+0x0008: 0x00       (PMTMR)
pmbase+0x0009: 0xff       (RESERVED)
pmbase+0x000a: 0xff       (RESERVED)
pmbase+0x000b: 0xff       (RESERVED)
pmbase+0x000c: 0xffff     (GPSTS)
pmbase+0x000e: 0xffff     (GPEN)
pmbase+0x0010: 0xabababab (PCNTRL)
pmbase+0x0018: 0x0000     (GLBSTS)
pmbase+0x001a: 0xffff     (RESERVED)
pmbase+0x001c: 0xffffffff (DEVSTS)
pmbase+0x0020: 0x0000     (GLBEN)
pmbase+0x0022: 0xff       (RESERVED)
pmbase+0x0023: 0xff       (RESERVED)
pmbase+0x0024: 0x00       (RESERVED)
pmbase+0x0025: 0x58       (RESERVED)
pmbase+0x0026: 0xff       (RESERVED)
pmbase+0x0027: 0xff       (RESERVED)
pmbase+0x0028: 0x00000000 (GLBCTL)
pmbase+0x002c: 0x00000000 (DEVCTL)
pmbase+0x0030: 0x00       (GPIREG 0)
pmbase+0x0031: 0x58       (GPIREG 1)
pmbase+0x0032: 0xff       (GPIREG 2)
pmbase+0x0033: 0xff       (GPIREG 3)
pmbase+0x0034: 0x00       (GPOREG 0)
pmbase+0x0035: 0x58       (GPOREG 1)
pmbase+0x0036: 0xff       (GPOREG 2)
pmbase+0x0037: 0xff       (GPOREG 3)



============= MCHBAR ============

This northbrigde does not have MCHBAR.



============= EPBAR =============

Error: Dumping EPBAR on this northbridge is not (yet) supported.



============= DMIBAR ============

Error: Dumping DMIBAR on this northbridge is not (yet) supported.


========= PCIEXBAR ========

Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.



===================== SHARED MSRs (All Cores) =====================
 MSR 0x00000010 = 0x000000F4:0x76D09572 (IA32_TIME_STAMP_COUNTER)
 MSR 0x00000017 = 0x40200000:0x00000000 (IA32_PLATFORM_ID)
 MSR 0x0000001B = 0x00000000:0xFEE00100 (IA32_APIC_BASE)
 MSR 0x0000002A = 0x00000000:0xC6C80000 (EBL_CR_POWERON)
 MSR 0x00000033 = 0x00000000:0x00000000 (TEST_CTL)
 (*) MSR 0x0000003F = 0xFFFFFFFF:0xFFFFFFFF (THERM_DIODE_OFFSET)
 MSR 0x0000008B = 0x0000000E:0x00000000 (IA32_BIOS_SIGN_ID)
 MSR 0x000000C1 = 0x00000000:0x00000000 (PERFCTR0)
 MSR 0x000000C2 = 0x00000000:0x00000000 (PERFCTR1)
 MSR 0x00000119 = 0x00000000:0x00200003 (BBL_CR_CTL)
 MSR 0x0000011E = 0x00000000:0x01344523 (BBL_CR_CTL3)
 MSR 0x00000179 = 0x00000000:0x00000005 (IA32_MCG_CAP)
 MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS)
 (*) MSR 0x00000198 = 0xFFFFFFFF:0xFFFFFFFF (IA32_PERF_STATUS)
 (*) MSR 0x00000199 = 0xFFFFFFFF:0xFFFFFFFF (IA32_PERF_CONTROL)
 (*) MSR 0x0000019A = 0xFFFFFFFF:0xFFFFFFFF (IA32_CLOCK_MODULATION)
 (*) MSR 0x000001A0 = 0xFFFFFFFF:0xFFFFFFFF (IA32_MISC_ENABLES)
 MSR 0x000001D9 = 0x00000000:0x00000001 (IA32_DEBUGCTL)
 MSR 0x00000200 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE0)
 MSR 0x00000201 = 0x0000000F:0xC0000800 (IA32_MTRR_PHYSMASK0)
 MSR 0x00000202 = 0x00000000:0xE4000001 (IA32_MTRR_PHYSBASE1)
 MSR 0x00000203 = 0x0000000F:0xFC000800 (IA32_MTRR_PHYSMASK1)
 MSR 0x00000204 = 0x00000000:0xD8000001 (IA32_MTRR_PHYSBASE2)
 MSR 0x00000205 = 0x0000000F:0xF8000800 (IA32_MTRR_PHYSMASK2)
 MSR 0x00000206 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE3)
 MSR 0x00000207 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK3)
 MSR 0x00000208 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE4)
 MSR 0x00000209 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK4)
 MSR 0x0000020A = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE5)
 MSR 0x0000020B = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK5)
 MSR 0x0000020C = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE6)
 MSR 0x0000020D = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK6)
 MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7)
 MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7)
 MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000)
 MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000)
 MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000)
 MSR 0x00000268 = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_C0000)
 MSR 0x00000269 = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_C8000)
 MSR 0x0000026A = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_D0000)
 MSR 0x0000026B = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_D8000)
 MSR 0x0000026C = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_E0000)
 MSR 0x0000026D = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_E8000)
 MSR 0x0000026E = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_F0000)
 MSR 0x0000026F = 0x00000005:0x05050505 (IA32_MTRR_FIX4K_F8000)
 MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE)
 MSR 0x00000400 = 0x00000000:0xC6C80000 (IA32_MC0_CTL)
 MSR 0x00000401 = 0x10000000:0x00000000 (IA32_MC0_STATUS)
 MSR 0x00000402 = 0x00000000:0x00000000 (IA32_MC0_ADDR)
 MSR 0x0000040C = 0x00000000:0x00000001 (IA32_MC4_CTL)
 MSR 0x0000040D = 0x00000000:0x00000000 (IA32_MC4_STATUS)
 (*) MSR 0x0000040E = 0xFFFFFFFF:0xFFFFFFFF (IA32_MC4_ADDR)

(*) Some MSRs could not be read. The marked values are unreliable.

Patch

Index: util/inteltool/cpu.c
===================================================================
--- util/inteltool/cpu.c	(revision 5976)
+++ util/inteltool/cpu.c	(working copy)
@@ -108,6 +108,7 @@ 
 		{ 0x008b, "IA32_BIOS_SIGN_ID" },
 		{ 0x00c1, "PERFCTR0" },
 		{ 0x00c2, "PERFCTR1" },
+		{ 0x0119, "BBL_CR_CTL" },
 		{ 0x011e, "BBL_CR_CTL3" },
 		{ 0x0179, "IA32_MCG_CAP" },
 		{ 0x017a, "IA32_MCG_STATUS" },
@@ -453,6 +454,10 @@ 
 	} cpu_t;
 
 	cpu_t cpulist[] = {
+		{ 0x00630, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
+		{ 0x00650, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
+		{ 0x00660, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
+		{ 0x00670, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
 		{ 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
 		{ 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
 		{ 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },