| Submitter | Tobias Diedrich |
|---|---|
| Date | 2010-10-21 00:53:36 |
| Message ID | <20101021005335.GA7626@yumi.tdiedrich.de> |
| Download | mbox | patch |
| Permalink | /patch/2154/ |
| State | New |
| Headers | show |
Comments
hi, i would like to suggest that put all of the log into the attachment. Put the patch into another attachment too. 2010/10/21 Tobias Diedrich <ranma+coreboot@tdiedrich.de<ranma%2Bcoreboot@tdiedrich.de> > > Hi, > > did you get somewhere with your M2V? > I'm looking into it right now, but I don't have the vt8237a docs. > Coreboot starts initializing HW, but it hangs during the bus scan... > Looks like it hangs while trying to scan the pcie bridge 00:02.0 > > > > coreboot-4.0-r5976M Thu Oct 21 02:30:11 CEST 2010 starting... > now booting... > Enabling routing table for node 00 done. > Enabling UP settings > Disabling read/write/fill probes for UP... done. > coherent_ht_finalize > done > core0 started: > now booting... All core 0 started > started ap apicid: > SBLink=00 > NC node|link=00 > 00entering optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > entering ht_optimize_link > pos=0x8a, unfiltered freq_cap=0x8075 > pos=0x8a, filtered freq_cap=0x75 > pos=0x6e, unfiltered freq_cap=0x75 > pos=0x6e, filtered freq_cap=0x75 > freq_cap1=0x75, freq_cap2=0x75 > dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 > dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 > width_cap1=0x11, width_cap2=0x11 > dev1 input ln_width1=0x4, ln_width2=0x4 > dev1 input width=0x1 > dev1 output ln_width1=0x4, ln_width2=0x4 > dev1 input|output width=0x11 > old dev1 input|output width=0x11 > dev2 input|output width=0x11 > old dev2 input|output width=0x11 > after ht_optimize_link for link pair 0, reset_needed=0x1 > after optimize_link_read_pointers_chain, reset_needed=0x1 > 01K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 > VIA HT caps: 0075 > 01ht reset - > soft reset > > > coreboot-4.0-r5976M Thu Oct 21 02:30:11 CEST 2010 starting... > now booting... > Enabling routing table for node 00 done. > Enabling UP settings > Disabling read/write/fill probes for UP... done. > coherent_ht_finalize > done > core0 started: > now booting... All core 0 started > started ap apicid: > SBLink=00 > NC node|link=00 > 00entering optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > entering ht_optimize_link > pos=0x8a, unfiltered freq_cap=0x8075 > pos=0x8a, filtered freq_cap=0x75 > pos=0x6e, unfiltered freq_cap=0x75 > pos=0x6e, filtered freq_cap=0x75 > freq_cap1=0x75, freq_cap2=0x75 > dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 > dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 > width_cap1=0x11, width_cap2=0x11 > dev1 input ln_width1=0x4, ln_width2=0x4 > dev1 input width=0x1 > dev1 output ln_width1=0x4, ln_width2=0x4 > dev1 input|output width=0x11 > old dev1 input|output width=0x11 > dev2 input|output width=0x11 > old dev2 input|output width=0x11 > after ht_optimize_link for link pair 0, reset_needed=0x0 > after optimize_link_read_pointers_chain, reset_needed=0x0 > 00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 > VIA HT caps: 0075 > 00after enable_fid_change > toggle LDTSTP# > done > Current fid_cur: 0x2, fid_max: 0xc > Requested fid_new: 0xc > FidVid table step fidvid: 0xc > toggle LDTSTP# > done > FidVid table step fidvid: 0xc > toggle LDTSTP# > done > FidVid table step fidvid: 0xc > toggle LDTSTP# > done > FidVid table step fidvid: 0xc > toggle LDTSTP# > done > FidVid table step fidvid: 0xc > toggle LDTSTP# > done > FidVid table step fidvid: 0xc > toggle LDTSTP# > done > FidVid table step fidvid: 0xc > toggle LDTSTP# > done > FidVid table step fidvid: 0xc > toggle LDTSTP# > done > toggle LDTSTP# > done > set vid failed for apicid =00 > set fid failed for apicid =00 > enable_smbus() > Ram1.00 > setting up CPU 00 northbridge registers > done. > Ram2.00 > sdram_set_spd_registers: paramx :000ceee8 > Enabling dual channel memory > Unbuffered > 266MHz > 266MHz > Interleaved > RAM end at 0x00800000 kB > Ram3 > Initializing memory: done > Setting variable MTRR 2, base: 0MB, range: 2048MB, type WB > Setting variable MTRR 3, base: 2048MB, range: 1024MB, type WB > Setting variable MTRR 4, base: 3072MB, range: 512MB, type WB > Setting variable MTRR 5, base: 3584MB, range: 256MB, type WB > Setting variable MTRR 6, base: 3840MB, range: 128MB, type WB > Setting variable MTRR 7, base: 3968MB, range: 64MB, type WB > DQS Training:RcvrEn:Pass1: 00 > CTLRMaxDelay=06 > done > DQS Training:DQSPos: 00 > TrainDQSRdWrPos: buf_a:000ce950 > TrainDQSPos: MutualCSPassW[48] :000ce828 > TrainDQSPos: MutualCSPassW[48] :000ce828 > TrainDQSPos: MutualCSPassW[48] :000ce828 > TrainDQSPos: MutualCSPassW[48] :000ce828 > TrainDQSPos: MutualCSPassW[48] :000ce828 > TrainDQSPos: MutualCSPassW[48] :000ce828 > TrainDQSPos: MutualCSPassW[48] :000ce828 > TrainDQSPos: MutualCSPassW[48] :000ce828 > TrainDQSPos: MutualCSPassW[48] :000ce828 > TrainDQSPos: MutualCSPassW[48] :000ce828 > TrainDQSPos: MutualCSPassW[48] :000ce828 > TrainDQSPos: MutualCSPassW[48] :000ce828 > done > DQS Training:RcvrEn:Pass2: 00 > CTLRMaxDelay=38 > done > DQS SAVE NVRAM: c2000 > Writing 111322 of size 4 to nvram pos: 0 > Writing 17181717 of size 4 to nvram pos: 4 > Writing 17181817 of size 4 to nvram pos: 8 > Writing 17 of size 1 to nvram pos: 12 > Writing 342f00 of size 4 to nvram pos: 13 > Writing 16161717 of size 4 to nvram pos: 17 > Writing 17161717 of size 4 to nvram pos: 21 > Writing 17 of size 1 to nvram pos: 25 > Writing 35 of size 1 to nvram pos: 26 > Writing 38 of size 1 to nvram pos: 27 > Writing 0 of size 1 to nvram pos: 28 > Writing 0 of size 1 to nvram pos: 29 > Writing 111322 of size 4 to nvram pos: 30 > Writing 17161617 of size 4 to nvram pos: 34 > Writing 17171818 of size 4 to nvram pos: 38 > Writing 18 of size 1 to nvram pos: 42 > Writing 342f00 of size 4 to nvram pos: 43 > Writing 16161615 of size 4 to nvram pos: 47 > Writing 18161616 of size 4 to nvram pos: 51 > Writing 16 of size 1 to nvram pos: 55 > Writing 35 of size 1 to nvram pos: 56 > Writing 38 of size 1 to nvram pos: 57 > Writing 0 of size 1 to nvram pos: 58 > Writing 0 of size 1 to nvram pos: 59 > Writing 34108099 of size 4 to nvram pos: 60 > DQS Training:tsc[00]=000000006852302d > DQS Training:tsc[01]=0000000069705232 > DQS Training:tsc[02]=000000006970523b > DQS Training:tsc[03]=00000000f0113e95 > DQS Training:tsc[04]=00000001021a6006 > Ram4 > v_esp=000cef28 > testx = 5a5a5a5a > Copying data from cache to RAM -- switching to use RAM as stack... Done > testx = 5a5a5a5a > Disabling cache as ram now > Clearing initial memory region: Done > Loading stage image. > Check CBFS header at fffffc6e > magic is 4f524243 > Found CBFS header at fffffc6e > Check fallback/romstage > CBFS: follow chain: fffc0000 + 38 + b461 + align -> fffcb4c0 > Check fallback/coreboot_ram > Stage: loading fallback/coreboot_ram @ 0x100000 (491520 bytes), entry @ > 0x100000 > Stage: done loading. > Jumping to image. > coreboot-4.0-r5976M Thu Oct 21 02:30:11 CEST 2010 booting... > Enumerating buses... > Show all devs...Before Device Enumeration. > Root Device: enabled 1 > APIC_CLUSTER: 0: enabled 1 > APIC: 00: enabled 1 > PCI_DOMAIN: 0000: enabled 1 > PCI: 00:18.0: enabled 1 > PCI: 00:00.0: enabled 1 > PCI: 00:0f.1: enabled 1 > PCI: 00:11.0: enabled 1 > I2C: 00:50: enabled 1 > I2C: 00:51: enabled 1 > I2C: 00:52: enabled 1 > I2C: 00:53: enabled 1 > PNP: 002e.0: enabled 1 > PNP: 002e.1: enabled 1 > PNP: 002e.2: enabled 1 > PNP: 002e.3: enabled 0 > PNP: 002e.4: enabled 1 > PNP: 002e.5: enabled 0 > PNP: 002e.6: enabled 0 > PNP: 002e.7: enabled 0 > PNP: 002e.8: enabled 0 > PNP: 002e.9: enabled 0 > PNP: 002e.a: enabled 0 > PCI: 00:12.0: enabled 0 > PCI: 00:18.1: enabled 1 > PCI: 00:18.2: enabled 1 > PCI: 00:18.3: enabled 1 > Compare with tree... > Root Device: enabled 1 > APIC_CLUSTER: 0: enabled 1 > APIC: 00: enabled 1 > PCI_DOMAIN: 0000: enabled 1 > PCI: 00:18.0: enabled 1 > PCI: 00:00.0: enabled 1 > PCI: 00:0f.1: enabled 1 > PCI: 00:11.0: enabled 1 > I2C: 00:50: enabled 1 > I2C: 00:51: enabled 1 > I2C: 00:52: enabled 1 > I2C: 00:53: enabled 1 > PNP: 002e.0: enabled 1 > PNP: 002e.1: enabled 1 > PNP: 002e.2: enabled 1 > PNP: 002e.3: enabled 0 > PNP: 002e.4: enabled 1 > PNP: 002e.5: enabled 0 > PNP: 002e.6: enabled 0 > PNP: 002e.7: enabled 0 > PNP: 002e.8: enabled 0 > PNP: 002e.9: enabled 0 > PNP: 002e.a: enabled 0 > PCI: 00:12.0: enabled 0 > PCI: 00:18.1: enabled 1 > PCI: 00:18.2: enabled 1 > PCI: 00:18.3: enabled 1 > scan_static_bus for Root Device > APIC_CLUSTER: 0 enabled > PCI_DOMAIN: 0000 enabled > APIC_CLUSTER: 0 scanning... > PCI: 00:18.3 siblings=0 > Found Rev E or Rev F later single core > CPU: APIC: 00 enabled > PCI_DOMAIN: 0000 scanning... > PCI: pci_scan_bus for bus 00 > PCI: 00:18.0 [1022/1100] bus ops > PCI: 00:18.0 [1022/1100] enabled > PCI: 00:18.1 [1022/1101] enabled > PCI: 00:18.2 [1022/1102] enabled > PCI: 00:18.3 [1022/1103] ops > PCI: 00:18.3 [1022/1103] enabled > PCI: Using configuration type 1 > PCI: 00:00.0 [1106/0351] enabled > Capability: type 0x01 @ 0x50 > Capability: type 0x08 @ 0x60 > flags: 0x0060 > PCI: 00:00.0 count: 0003 static_count: 0013 > PCI: 00:00.0 [1106/0351] enabled next_unitid: 0013 > PCI: pci_scan_bus for bus 00 > PCI: 00:00.0 [1106/0351] enabled > malloc Enter, size 68, free_mem_ptr 00138000 > malloc 00138000 > PCI: 00:00.1 [1106/1351] enabled > malloc Enter, size 68, free_mem_ptr 00138044 > malloc 00138044 > PCI: 00:00.2 [1106/2351] enabled > malloc Enter, size 68, free_mem_ptr 00138088 > malloc 00138088 > PCI: 00:00.3 [1106/3351] enabled > malloc Enter, size 68, free_mem_ptr 001380cc > malloc 001380cc > PCI: 00:00.4 [1106/4351] enabled > malloc Enter, size 68, free_mem_ptr 00138110 > malloc 00138110 > PCI: 00:00.5 [1106/5351] enabled > malloc Enter, size 68, free_mem_ptr 00138154 > malloc 00138154 > PCI: 00:00.6 [1106/6238] enabled > malloc Enter, size 68, free_mem_ptr 00138198 > malloc 00138198 > PCI: 00:00.7 [1106/7351] enabled > malloc Enter, size 68, free_mem_ptr 001381dc > malloc 001381dc > PCI: 00:01.0 [1106/b188] bus ops > B188 device dump > 00: 06 11 88 b1 07 00 30 02 00 00 04 06 00 00 01 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 20 02 > 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 70 00 00 00 00 00 00 00 00 00 16 00 > 40: 91 40 00 44 31 3a 88 b1 00 00 00 00 00 00 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 0e 70 35 00 07 02 00 1f 00 00 00 00 28 00 00 00 > 90: 80 00 00 00 00 08 01 00 00 00 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: bf 63 08 00 00 00 00 00 00 00 1f c4 00 04 00 00 > c0: 08 00 0b ff 00 00 00 00 00 00 00 00 00 00 00 00 > d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > PCI: 00:01.0 [1106/b188] enabled > malloc Enter, size 68, free_mem_ptr 00138220 > malloc 00138220 > PCI: 00:02.0 [1106/a238] bus ops > Configuring PCIe PEG > 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 > 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 > 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 18 00 > 50: 00 00 20 00 60 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 > 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 > b0: 0c 12 c0 81 00 00 03 00 00 00 00 00 00 00 00 00 > c0: 43 02 27 8a 44 44 44 44 44 44 44 44 00 00 00 00 > d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 > e0: 00 04 84 50 c2 00 00 00 8f 00 97 00 00 00 00 00 > f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 > 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 > 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 > 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 18 00 > 50: 00 00 20 00 60 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 > 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 01 44 30 f1 7c ff 7f 04 00 00 00 00 00 00 00 00 > b0: 0c f0 c0 81 00 00 03 00 01 00 00 00 00 00 00 00 > c0: 43 02 27 8a 44 44 44 44 44 44 44 44 00 00 00 00 > d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 > e0: 00 0b 84 50 c2 00 00 00 8f 00 97 00 00 00 00 00 > f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 > PCI: 00:02.0 [1106/a238] enabled > malloc Enter, size 68, free_mem_ptr 00138264 > malloc 00138264 > PCI: 00:03.0 [1106/c238] bus ops > Configuring PCIe PEXs > 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 81 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 > 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 > 40: 10 68 41 01 c1 0e 00 00 00 00 10 00 41 0c 18 01 > 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 > 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 > b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00 > c0: 43 4a 27 8a 44 44 00 00 00 00 00 00 00 00 00 00 > d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 > e0: 00 00 00 22 28 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 > 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 81 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 > 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 > 40: 10 68 41 01 c1 0e 00 00 00 00 10 00 41 0c 18 01 > 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 > 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 > b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00 > c0: 43 4a 27 8a 44 44 00 00 00 00 00 00 00 00 00 00 > d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 > e0: 00 0b 00 22 28 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 > PCI: 00:03.0 [1106/c238] enabled > malloc Enter, size 68, free_mem_ptr 001382a8 > malloc 001382a8 > PCI: 00:03.1 [1106/d238] bus ops > Configuring PCIe PEXs > 00: 06 11 38 d2 00 00 10 00 00 00 04 06 00 00 81 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 > 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 02 00 00 > 40: 10 68 41 01 81 0f 00 00 00 00 10 00 11 0c 18 02 > 50: 10 00 00 00 60 00 00 00 00 00 48 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 > 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 > b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00 > c0: 03 18 00 8a 44 44 44 44 00 00 00 00 00 00 00 00 > d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 > e0: 00 0f 00 02 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 > 00: 06 11 38 d2 00 00 10 00 00 00 04 06 00 00 81 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 > 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 02 00 00 > 40: 10 68 41 01 81 0f 00 00 00 00 10 00 11 0c 18 02 > 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 > 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 > b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00 > c0: 03 18 00 8a 44 44 44 44 00 00 00 00 00 00 00 00 > d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 > e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 > PCI: 00:03.1 [1106/d238] enabled > malloc Enter, size 68, free_mem_ptr 001382ec > malloc 001382ec > PCI: 00:03.2 [1106/e238] bus ops > Configuring PCIe PEXs > 00: 06 11 38 e2 00 00 10 00 00 00 04 06 00 00 81 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 > 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 03 00 00 > 40: 10 68 41 01 81 0f 00 00 00 00 10 00 11 0c 18 03 > 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 > 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 > b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 8a 04 00 00 00 00 00 00 00 00 00 00 00 > d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 > e0: 00 0c 00 02 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00: 06 11 38 e2 00 00 10 00 00 00 04 06 00 00 81 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 > 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 03 00 00 > 40: 10 68 41 01 81 0f 00 00 00 00 10 00 11 0c 18 03 > 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 > 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 > b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 8a 04 00 00 00 00 00 00 00 00 00 00 00 > d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 > e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > PCI: 00:03.2 [1106/e238] enabled > malloc Enter, size 68, free_mem_ptr 00138330 > malloc 00138330 > PCI: 00:03.3 [1106/f238] bus ops > Configuring PCIe PEXs > 00: 06 11 38 f2 00 00 10 00 00 00 04 06 00 00 81 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 > 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 04 00 00 > 40: 10 68 41 01 01 0e 00 00 00 00 10 00 11 0c 18 04 > 50: 10 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 > 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 > b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 8a 04 00 00 00 00 00 00 00 00 00 00 00 > d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 > e0: 00 09 00 02 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00: 06 11 38 f2 00 00 10 00 00 00 04 06 00 00 81 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 > 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 > 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 04 00 00 > 40: 10 68 41 01 01 0e 00 00 00 00 10 00 11 0c 18 04 > 50: 00 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 > 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 > b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00 > c0: 00 00 00 8a 04 00 00 00 00 00 00 00 00 00 00 00 > d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 > e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > PCI: 00:03.3 [1106/f238] enabled > malloc Enter, size 68, free_mem_ptr 00138374 > malloc 00138374 > PCI: 00:0b.0 [102b/0519] enabled > malloc Enter, size 68, free_mem_ptr 001383b8 > malloc 001383b8 > PCI: 00:0f.0 [1106/0591] enabled > PCI: 00:0f.1 [1106/0571] ops > PCI: 00:0f.1 [1106/0571] enabled > malloc Enter, size 68, free_mem_ptr 001383fc > malloc 001383fc > PCI: 00:10.0 [1106/3038] ops > PCI: 00:10.0 [1106/3038] enabled > malloc Enter, size 68, free_mem_ptr 00138440 > malloc 00138440 > PCI: 00:10.1 [1106/3038] ops > PCI: 00:10.1 [1106/3038] enabled > malloc Enter, size 68, free_mem_ptr 00138484 > malloc 00138484 > PCI: 00:10.2 [1106/3038] ops > PCI: 00:10.2 [1106/3038] enabled > malloc Enter, size 68, free_mem_ptr 001384c8 > malloc 001384c8 > PCI: 00:10.3 [1106/3038] ops > PCI: 00:10.3 [1106/3038] enabled > malloc Enter, size 68, free_mem_ptr 0013850c > malloc 0013850c > PCI: 00:10.4 [1106/3104] ops > PCI: 00:10.4 [1106/3104] enabled > PCI: 00:11.0 [1106/3337] enabled > malloc Enter, size 68, free_mem_ptr 00138550 > malloc 00138550 > PCI: 00:11.7 [1106/287e] ops > PCI: 00:11.7 [1106/287e] enabled > do_pci_scan_bridge for PCI: 00:01.0 > malloc Enter, size 24, free_mem_ptr 00138594 > malloc 00138594 > PCI: pci_scan_bus for bus 01 > PCI: pci_scan_bus returning with max=001 > do_pci_scan_bridge returns max 1 > do_pci_scan_bridge for PCI: 00:02.0 > malloc Enter, size 24, free_mem_ptr 001385ac > malloc 001385ac > PCI: pci_scan_bus for bus 02 > [hangs here] > > > Patch so far (mostly copied from a8v-e_se and m2v-mx_se): > > Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c > =================================================================== > --- src/southbridge/via/vt8237r/vt8237r_early_smbus.c (revision 5976) > +++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c (working copy) > @@ -142,6 +142,7 @@ > device_t dev; > int loops; > > + print_debug("enable_smbus()\n"); > /* Power management controller */ > dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, > PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); > @@ -149,8 +150,13 @@ > /* Power management controller */ > dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, > PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); > - if (dev == PCI_DEV_INVALID) > - die("Power management controller not found\n"); > + if (dev == PCI_DEV_INVALID) { > + /* Power management controller */ > + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, > + > PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); > + if (dev == PCI_DEV_INVALID) > + die("Power management controller not > found\n"); > + } > } > > /* Make sure the RTC power well is up before touching smbus. */ > @@ -242,15 +248,20 @@ > if (dev == PCI_DEV_INVALID) { > /* Power management controller */ > dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, > + PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); > + } > + if (dev == PCI_DEV_INVALID) { > + /* Power management controller */ > + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, > PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); > - if (dev == PCI_DEV_INVALID) > - return; > > devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, > PCI_DEVICE_ID_VIA_VT8237_VLINK), > 0); > > - if (devctl == PCI_DEV_INVALID) > + if (devctl == PCI_DEV_INVALID) { > + print_err("vt8237_sb_enable_fid_vid() failed\n"); > return; > + } > > /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ > pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); > @@ -297,7 +308,7 @@ > if (dev == PCI_DEV_INVALID) { > /* Power management controller */ > dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, > - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); > + PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); > if (dev == PCI_DEV_INVALID) > return; > } > @@ -321,7 +332,7 @@ > if (dev == PCI_DEV_INVALID) { > /* Power management controller */ > dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, > - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); > + PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); > if (dev == PCI_DEV_INVALID) > die("Power management controller not found\n"); > } > Index: src/include/device/pci_ids.h > =================================================================== > --- src/include/device/pci_ids.h (revision 5976) > +++ src/include/device/pci_ids.h (working copy) > @@ -1219,6 +1219,7 @@ > #define PCI_DEVICE_ID_VIA_K8T890CE_BR 0xb188 > #define PCI_DEVICE_ID_VIA_VT6420_SATA 0x3149 > #define PCI_DEVICE_ID_VIA_VT8237R_LPC 0x3227 > +#define PCI_DEVICE_ID_VIA_VT8237A_LPC 0x3337 > #define PCI_DEVICE_ID_VIA_VT8237S_LPC 0x3372 > #define PCI_DEVICE_ID_VIA_VT8237_SATA 0x5372 > #define PCI_DEVICE_ID_VIA_VT8237_VLINK 0x287e > Index: src/mainboard/asus/Kconfig > =================================================================== > --- src/mainboard/asus/Kconfig (revision 5976) > +++ src/mainboard/asus/Kconfig (working copy) > @@ -25,6 +25,8 @@ > bool "A8N-E" > config BOARD_ASUS_A8V_E_SE > bool "A8V-E SE" > +config BOARD_ASUS_M2V > + bool "M2V" > config BOARD_ASUS_M2V_MX_SE > bool "M2V-MX SE" > config BOARD_ASUS_M4A785M > @@ -50,6 +52,7 @@ > > source "src/mainboard/asus/a8n_e/Kconfig" > source "src/mainboard/asus/a8v-e_se/Kconfig" > +source "src/mainboard/asus/m2v/Kconfig" > source "src/mainboard/asus/m2v-mx_se/Kconfig" > source "src/mainboard/asus/m4a785-m/Kconfig" > source "src/mainboard/asus/mew-am/Kconfig" > diff -Naru src/mainboard/asus/m2v.none/acpi_tables.c > src/mainboard/asus/m2v/acpi_tables.c > --- src/mainboard/asus/m2v.none/acpi_tables.c 1970-01-01 > 01:00:00.000000000 +0100 > +++ src/mainboard/asus/m2v/acpi_tables.c 2010-10-20 > 19:17:51.000000000 +0200 > @@ -0,0 +1,156 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Written by Stefan Reinauer <stepan@openbios.org>. > + * ACPI FADT, FACS, and DSDT table support added by > + * > + * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org> > + * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> > + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > + > +#include <console/console.h> > +#include <string.h> > +#include <arch/acpi.h> > +#include <arch/smp/mpspec.h> > +#include <arch/ioapic.h> > +#include <device/device.h> > +#include <device/pci_ids.h> > +#include "southbridge/via/vt8237r/vt8237r.h" > +#include "southbridge/via/k8t890/k8t890.h" > + > +extern const unsigned char AmlCode[]; > + > +unsigned long acpi_fill_mcfg(unsigned long current) > +{ > + device_t dev; > + struct resource *res; > + > + dev = dev_find_device(PCI_VENDOR_ID_VIA, > PCI_DEVICE_ID_VIA_K8T890CE_5, 0); > + if (!dev) > + return current; > + > + res = find_resource(dev, K8T890_MMCONFIG_MBAR); > + if (res) { > + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t > *) > + current, res->base, 0x0, 0x0, 0xff); > + } > + return current; > +} > + > +unsigned long acpi_fill_madt(unsigned long current) > +{ > + unsigned int gsi_base = 0x18; > + > + /* Create all subtables for processors. */ > + current = acpi_create_madt_lapics(current); > + > + /* Write SB IOAPIC. */ > + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, > + VT8237R_APIC_ID, IO_APIC_ADDR, 0); > + > + /* Write NB IOAPIC. */ > + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, > + K8T890_APIC_ID, K8T890_APIC_BASE, > gsi_base); > + > + /* IRQ9 ACPI active low. */ > + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) > + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | > MP_IRQ_POLARITY_LOW); > + > + /* IRQ0 -> APIC IRQ2. */ > + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) > + current, 0, 0, 2, 0x0); > + > + /* Create all subtables for processors. */ > + current = acpi_create_madt_lapic_nmis(current, > + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); > + > + return current; > +} > + > +unsigned long write_acpi_tables(unsigned long start) > +{ > + unsigned long current; > + acpi_rsdp_t *rsdp; > + acpi_srat_t *srat; > + acpi_rsdt_t *rsdt; > + acpi_madt_t *madt; > + acpi_mcfg_t *mcfg; > + acpi_fadt_t *fadt; > + acpi_facs_t *facs; > + acpi_header_t *dsdt; > + > + /* Align ACPI tables to 16 byte. */ > + start = (start + 0x0f) & -0x10; > + current = start; > + > + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); > + > + /* We need at least an RSDP and an RSDT table. */ > + rsdp = (acpi_rsdp_t *) current; > + current += sizeof(acpi_rsdp_t); > + rsdt = (acpi_rsdt_t *) current; > + current += sizeof(acpi_rsdt_t); > + > + /* Clear all table memory. */ > + memset((void *) start, 0, current - start); > + > + acpi_write_rsdp(rsdp, rsdt, NULL); > + acpi_write_rsdt(rsdt); > + > + /* We explicitly add these tables later on: */ > + printk(BIOS_DEBUG, "ACPI: * FACS\n"); > + facs = (acpi_facs_t *) current; > + current += sizeof(acpi_facs_t); > + acpi_create_facs(facs); > + > + dsdt = (acpi_header_t *)current; > + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); > + current += dsdt->length; > + memcpy(dsdt, &AmlCode, dsdt->length); > + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ > + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); > + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, > + dsdt->length); > + printk(BIOS_DEBUG, "ACPI: * FADT\n"); > + > + fadt = (acpi_fadt_t *) current; > + current += sizeof(acpi_fadt_t); > + > + acpi_create_fadt(fadt, facs, dsdt); > + acpi_add_table(rsdp, fadt); > + > + /* If we want to use HPET timers Linux wants it in MADT. */ > + printk(BIOS_DEBUG, "ACPI: * MADT\n"); > + madt = (acpi_madt_t *) current; > + acpi_create_madt(madt); > + current += madt->header.length; > + acpi_add_table(rsdp, madt); > + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); > + mcfg = (acpi_mcfg_t *) current; > + acpi_create_mcfg(mcfg); > + current += mcfg->header.length; > + acpi_add_table(rsdp, mcfg); > + > + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); > + srat = (acpi_srat_t *) current; > + acpi_create_srat(srat); > + current += srat->header.length; > + acpi_add_table(rsdp, srat); > + > + printk(BIOS_INFO, "ACPI: done.\n"); > + return current; > +} > diff -Naru src/mainboard/asus/m2v.none/chip.h src/mainboard/asus/m2v/chip.h > --- src/mainboard/asus/m2v.none/chip.h 1970-01-01 01:00:00.000000000 +0100 > +++ src/mainboard/asus/m2v/chip.h 2010-10-20 19:17:51.000000000 +0200 > @@ -0,0 +1,22 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > + > +extern struct chip_operations mainboard_ops; > + > +struct mainboard_config {}; > diff -Naru src/mainboard/asus/m2v.none/cmos.layout > src/mainboard/asus/m2v/cmos.layout > --- src/mainboard/asus/m2v.none/cmos.layout 1970-01-01 > 01:00:00.000000000 +0100 > +++ src/mainboard/asus/m2v/cmos.layout 2010-10-20 19:17:51.000000000 +0200 > @@ -0,0 +1,98 @@ > +entries > + > +#start-bit length config config-ID name > +#0 8 r 0 seconds > +#8 8 r 0 alarm_seconds > +#16 8 r 0 minutes > +#24 8 r 0 alarm_minutes > +#32 8 r 0 hours > +#40 8 r 0 alarm_hours > +#48 8 r 0 day_of_week > +#56 8 r 0 day_of_month > +#64 8 r 0 month > +#72 8 r 0 year > +#80 4 r 0 rate_select > +#84 3 r 0 REF_Clock > +#87 1 r 0 UIP > +#88 1 r 0 auto_switch_DST > +#89 1 r 0 24_hour_mode > +#90 1 r 0 binary_values_enable > +#91 1 r 0 square-wave_out_enable > +#92 1 r 0 update_finished_enable > +#93 1 r 0 alarm_interrupt_enable > +#94 1 r 0 periodic_interrupt_enable > +#95 1 r 0 disable_clock_updates > +#96 288 r 0 temporary_filler > +0 384 r 0 reserved_memory > +384 1 e 4 boot_option > +385 1 e 4 last_boot > +386 1 e 1 ECC_memory > +388 4 r 0 reboot_bits > +392 3 e 5 baud_rate > +395 1 e 1 hw_scrubber > +396 1 e 1 interleave_chip_selects > +397 2 e 8 max_mem_clock > +399 1 e 2 multi_core > +400 1 e 1 power_on_after_fail > +412 4 e 6 debug_level > +416 4 e 7 boot_first > +420 4 e 7 boot_second > +424 4 e 7 boot_third > +428 4 h 0 boot_index > +432 8 h 0 boot_countdown > +440 4 e 9 slow_cpu > +444 1 e 1 nmi > +445 1 e 1 iommu > +728 256 h 0 user_data > +984 16 h 0 check_sum > +# Reserve the extended AMD configuration registers > +1000 24 r 0 amd_reserved > + > + > + > +enumerations > + > +#ID value text > +1 0 Disable > +1 1 Enable > +2 0 Enable > +2 1 Disable > +4 0 Fallback > +4 1 Normal > +5 0 115200 > +5 1 57600 > +5 2 38400 > +5 3 19200 > +5 4 9600 > +5 5 4800 > +5 6 2400 > +5 7 1200 > +6 6 Notice > +6 7 Info > +6 8 Debug > +6 9 Spew > +7 0 Network > +7 1 HDD > +7 2 Floppy > +7 8 Fallback_Network > +7 9 Fallback_HDD > +7 10 Fallback_Floppy > +#7 3 ROM > +8 0 DDR400 > +8 1 DDR333 > +8 2 DDR266 > +8 3 DDR200 > +9 0 off > +9 1 87.5% > +9 2 75.0% > +9 3 62.5% > +9 4 50.0% > +9 5 37.5% > +9 6 25.0% > +9 7 12.5% > + > +checksums > + > +checksum 392 983 984 > + > + > diff -Naru src/mainboard/asus/m2v.none/devicetree.cb > src/mainboard/asus/m2v/devicetree.cb > --- src/mainboard/asus/m2v.none/devicetree.cb 1970-01-01 > 01:00:00.000000000 +0100 > +++ src/mainboard/asus/m2v/devicetree.cb 2010-10-21 > 01:50:56.000000000 +0200 > @@ -0,0 +1,75 @@ > +chip northbridge/amd/amdk8/root_complex # Root complex > + device lapic_cluster 0 on # APIC cluster > + chip cpu/amd/socket_AM2 # CPU > + device lapic 0 on end # APIC > + end > + end > + device pci_domain 0 on # PCI domain > + chip northbridge/amd/amdk8 # mc0 > + device pci 18.0 on # Northbridge > + # Devices on link 0, link 0 == LDT 0 > + chip southbridge/via/vt8237r # Southbridge > + register "ide0_enable" = "1" # Enable IDE channel 0 > + register "ide1_enable" = "1" # Enable IDE channel 1 > + register "ide0_80pin_cable" = "1" # 80pin cable on IDE > channel 0 > + register "ide1_80pin_cable" = "1" # 80pin cable on IDE > channel 1 > + register "fn_ctrl_lo" = "0xc0" # Enable SB functions > + register "fn_ctrl_hi" = "0x0d" # Enable SB functions > + device pci 0.0 on end # HT > + device pci f.1 on end # IDE > + device pci 11.0 on # LPC > + chip drivers/generic/generic # DIMM 0-0-0 > + device i2c 50 on end > + end > + chip drivers/generic/generic # DIMM 0-0-1 > + device i2c 51 on end > + end > + chip drivers/generic/generic # DIMM 0-1-0 > + device i2c 52 on end > + end > + chip drivers/generic/generic # DIMM 0-1-1 > + device i2c 53 on end > + end > + chip superio/ite/it8712f # Super I/O > + device pnp 2e.0 on # Floppy > + io 0x60 = 0x3f0 > + irq 0x70 = 6 > + drq 0x74 = 2 > + end > + device pnp 2e.1 on # Parallel port > + io 0x60 = 0x378 > + irq 0x70 = 7 > + drq 0x74 = 3 > + end > + device pnp 2e.2 on # Com1 > + io 0x60 = 0x3f8 > + irq 0x70 = 4 > + end > + device pnp 2e.3 off # Com2 (N/A on this board) > + io 0x60 = 0x2f8 > + irq 0x70 = 3 > + end > + device pnp 2e.4 on # Environment controller > + io 0x60 = 0x290 > + io 0x62 = 0x230 > + irq 0x70 = 0x00 > + end > + device pnp 2e.5 off end # PS/2 keyboard > + device pnp 2e.6 off end # PS/2 mouse > + device pnp 2e.7 off end # GPIO config > + device pnp 2e.8 off end # Midi port > + device pnp 2e.9 off end # Game port > + device pnp 2e.a off end # IR > + end > + end > + device pci 12.0 off end # VIA LAN (off, other chip > used) > + end > + chip southbridge/via/k8t890 # "Southbridge" K8T890 > + end > + end > + device pci 18.1 on end > + device pci 18.2 on end > + device pci 18.3 on end > + end > + end > +end > diff -Naru src/mainboard/asus/m2v.none/dsdt.asl > src/mainboard/asus/m2v/dsdt.asl > --- src/mainboard/asus/m2v.none/dsdt.asl 1970-01-01 > 01:00:00.000000000 +0100 > +++ src/mainboard/asus/m2v/dsdt.asl 2010-10-20 19:17:51.000000000 +0200 > @@ -0,0 +1,211 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com> > + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > + > +/* > + * ISA portions taken from QEMU acpi-dsdt.dsl. > + */ > + > +DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) > +{ > + /* Define the main processor.*/ > + Scope (\_PR) > + { > + Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {} > + Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {} > + } > + > + /* For now only define 2 power states: > + * - S0 which is fully on > + * - S5 which is soft off > + * Any others would involve declaring the wake up methods. > + */ > + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) > + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) > + > + /* Root of the bus hierarchy */ > + Scope (\_SB) > + { > + /* Top PCI device */ > + Device (PCI0) > + { > + Name (_HID, EisaId ("PNP0A03")) > + Name (_ADR, 0x00) > + Name (_UID, 0x00) > + Name (_BBN, 0x00) > + > + /* PCI Routing Table */ > + /* aaa */ > + Name (_PRT, Package () { > + Package (0x04) { 0x000BFFFF, 0x00, 0x00, > 0x10 }, /* Slot 0xB */ > + Package (0x04) { 0x000BFFFF, 0x01, 0x00, > 0x11 }, > + Package (0x04) { 0x000BFFFF, 0x02, 0x00, > 0x12 }, > + Package (0x04) { 0x000BFFFF, 0x03, 0x00, > 0x13 }, > + Package (0x04) { 0x000CFFFF, 0x00, 0x00, > 0x11 }, /* Slot 0xC */ > + Package (0x04) { 0x000CFFFF, 0x01, 0x00, > 0x12 }, > + Package (0x04) { 0x000CFFFF, 0x02, 0x00, > 0x13 }, > + Package (0x04) { 0x000CFFFF, 0x03, 0x00, > 0x10 }, > + Package (0x04) { 0x000DFFFF, 0x00, 0x00, > 0x12 }, /* Slot 0xD */ > + Package (0x04) { 0x000DFFFF, 0x01, 0x00, > 0x13 }, > + Package (0x04) { 0x000DFFFF, 0x02, 0x00, > 0x10 }, > + Package (0x04) { 0x000DFFFF, 0x03, 0x00, > 0x11 }, > + Package (0x04) { 0x000FFFFF, 0x01, 0x00, > 0x14 }, /* 0xf SATA IRQ 20 */ > + Package (0x04) { 0x000FFFFF, 0x00, 0x00, > 0x14 }, /* 0xf Native IDE IRQ 20 */ > + Package (0x04) { 0x0010FFFF, 0x00, 0x00, > 0x15 }, /* USB routing */ > + Package (0x04) { 0x0010FFFF, 0x01, 0x00, > 0x15 }, > + Package (0x04) { 0x0010FFFF, 0x02, 0x00, > 0x15 }, > + Package (0x04) { 0x0010FFFF, 0x03, 0x00, > 0x15 }, > + Package (0x04) { 0x0011FFFF, 0x02, 0x00, > 0x16 }, /* AC97, MC97 */ > + Package (0x04) { 0x0002FFFF, 0x00, 0x00, > 0x1B }, /* PCIE16 bridge IRQ27 */ > + Package (0x04) { 0x0002FFFF, 0x01, 0x00, > 0x1B }, > + Package (0x04) { 0x0002FFFF, 0x02, 0x00, > 0x1B }, > + Package (0x04) { 0x0002FFFF, 0x03, 0x00, > 0x1B }, > + Package (0x04) { 0x0003FFFF, 0x00, 0x00, > 0x1F }, /* PCIE bridge IRQ31 */ > + Package (0x04) { 0x0003FFFF, 0x01, 0x00, > 0x23 }, /* IRQ36 */ > + Package (0x04) { 0x0003FFFF, 0x02, 0x00, > 0x27 }, /* IRQ39 */ > + Package (0x04) { 0x0003FFFF, 0x03, 0x00, > 0x2B } /* IRQ43 */ > + }) > + > + Device (PEGG) > + { > + Name (_ADR, 0x00020000) > + Name (_UID, 0x00) > + Name (_BBN, 0x02) > + Name (_PRT, Package () { > + Package (0x04) { 0x0000FFFF, 0x00, > 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ > + Package (0x04) { 0x0000FFFF, 0x01, > 0x00, 0x19 }, > + Package (0x04) { 0x0000FFFF, 0x02, > 0x00, 0x1A }, > + Package (0x04) { 0x0000FFFF, 0x03, > 0x00, 0x1B }, > + }) > + } > + > + Device (PEX0) > + { > + Name (_ADR, 0x00030000) > + Name (_UID, 0x00) > + Name (_BBN, 0x03) > + Name (_PRT, Package () { > + Package (0x04) { 0x0000FFFF, 0x00, > 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ > + Package (0x04) { 0x0000FFFF, 0x01, > 0x00, 0x1D }, > + Package (0x04) { 0x0000FFFF, 0x02, > 0x00, 0x1E }, > + Package (0x04) { 0x0000FFFF, 0x03, > 0x00, 0x1F }, > + }) > + } > + > + Device (PEX1) > + { > + Name (_ADR, 0x00030001) > + Name (_UID, 0x00) > + Name (_BBN, 0x04) > + Name (_PRT, Package () { > + Package (0x04) { 0x0000FFFF, 0x00, > 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ > + Package (0x04) { 0x0000FFFF, 0x01, > 0x00, 0x21 }, > + Package (0x04) { 0x0000FFFF, 0x02, > 0x00, 0x22 }, > + Package (0x04) { 0x0000FFFF, 0x03, > 0x00, 0x23 }, > + }) > + } > + > + Device (PEX2) > + { > + Name (_ADR, 0x00030002) > + Name (_UID, 0x00) > + Name (_BBN, 0x05) > + Name (_PRT, Package () { > + Package (0x04) { 0x0000FFFF, 0x00, > 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ > + Package (0x04) { 0x0000FFFF, 0x01, > 0x00, 0x25 }, > + Package (0x04) { 0x0000FFFF, 0x02, > 0x00, 0x26 }, > + Package (0x04) { 0x0000FFFF, 0x03, > 0x00, 0x27 }, > + }) > + } > + > + Device (PEX3) > + { > + Name (_ADR, 0x00030003) > + Name (_UID, 0x00) > + Name (_BBN, 0x06) > + Name (_PRT, Package () { > + Package (0x04) { 0x0000FFFF, 0x00, > 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ > + Package (0x04) { 0x0000FFFF, 0x01, > 0x00, 0x29 }, > + Package (0x04) { 0x0000FFFF, 0x02, > 0x00, 0x2A }, > + Package (0x04) { 0x0000FFFF, 0x03, > 0x00, 0x2B }, > + }) > + } > + > + Device (ISA) { > + Name (_ADR, 0x00110000) > + > + /* PS/2 keyboard (seems to be important for > WinXP install) */ > + Device (KBD) > + { > + Name (_HID, EisaId ("PNP0303")) > + Method (_STA, 0, NotSerialized) > + { > + Return (0x0f) > + } > + Method (_CRS, 0, NotSerialized) > + { > + Name (TMP, ResourceTemplate > () { > + IO (Decode16, > 0x0060, 0x0060, 0x01, 0x01) > + IO (Decode16, > 0x0064, 0x0064, 0x01, 0x01) > + IRQNoFlags () {1} > + }) > + Return (TMP) > + } > + } > + > + /* PS/2 mouse */ > + Device (MOU) > + { > + Name (_HID, EisaId ("PNP0F13")) > + Method (_STA, 0, NotSerialized) > + { > + Return (0x0f) > + } > + Method (_CRS, 0, NotSerialized) > + { > + Name (TMP, ResourceTemplate > () { > + IRQNoFlags () {12} > + }) > + Return (TMP) > + } > + } > + > + /* PS/2 floppy controller */ > + Device (FDC0) > + { > + Name (_HID, EisaId ("PNP0700")) > + Method (_STA, 0, NotSerialized) > + { > + Return (0x0f) > + } > + Method (_CRS, 0, NotSerialized) > + { > + Name (BUF0, > ResourceTemplate () { > + IO (Decode16, > 0x03F2, 0x03F2, 0x00, 0x04) > + IO (Decode16, > 0x03F7, 0x03F7, 0x00, 0x01) > + IRQNoFlags () {6} > + DMA (Compatibility, > NotBusMaster, Transfer8) {2} > + }) > + Return (BUF0) > + } > + } > + } > + } > + } > +} > diff -Naru src/mainboard/asus/m2v.none/Kconfig > src/mainboard/asus/m2v/Kconfig > --- src/mainboard/asus/m2v.none/Kconfig 1970-01-01 01:00:00.000000000 +0100 > +++ src/mainboard/asus/m2v/Kconfig 2010-10-20 22:52:31.000000000 +0200 > @@ -0,0 +1,79 @@ > +if BOARD_ASUS_M2V > + > +config BOARD_SPECIFIC_OPTIONS # dummy > + def_bool y > + select ARCH_X86 > + select CPU_AMD_SOCKET_AM2 > + select DIMM_DDR2 > + select K8_HT_FREQ_1G_SUPPORT > + select NORTHBRIDGE_AMD_AMDK8 > + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX > + select SOUTHBRIDGE_VIA_VT8237R > + select SOUTHBRIDGE_VIA_K8T890 > + select SUPERIO_ITE_IT8712F > + select CACHE_AS_RAM > + select HAVE_OPTION_TABLE > + select HAVE_ACPI_TABLES > + select HAVE_MP_TABLE > + select BOARD_ROMSIZE_KB_512 > + select RAMINIT_SYSINFO > + select TINY_BOOTBLOCK > +# select HAVE_MAINBOARD_RESOURCES > + > +config MAINBOARD_DIR > + string > + default asus/m2v > + > +config DCACHE_RAM_BASE > + hex > + default 0xcc000 > + > +config DCACHE_RAM_SIZE > + hex > + default 0x4000 > + > +config DCACHE_RAM_GLOBAL_VAR_SIZE > + hex > + default 0x1000 > + > +config APIC_ID_OFFSET > + hex > + default 0x10 > + > +config SB_HT_CHAIN_ON_BUS0 > + int > + default 1 > + > +config MAINBOARD_PART_NUMBER > + string > + default "M2V" > + > +config HW_MEM_HOLE_SIZEK > + hex > + default 0 > + > +config MAX_CPUS > + int > + default 2 > + > +config MAX_PHYSICAL_CPUS > + int > + default 1 > + > +config HEAP_SIZE > + hex > + default 0x40000 > + > +config HT_CHAIN_END_UNITID_BASE > + hex > + default 0x20 > + > +config HT_CHAIN_UNITID_BASE > + hex > + default 0x0 > + > +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID > + hex > + default 0x1043 > + > +endif # BOARD_ASUS_M2V > diff -Naru src/mainboard/asus/m2v.none/mainboard.c > src/mainboard/asus/m2v/mainboard.c > --- src/mainboard/asus/m2v.none/mainboard.c 1970-01-01 > 01:00:00.000000000 +0100 > +++ src/mainboard/asus/m2v/mainboard.c 2010-10-20 19:57:44.000000000 +0200 > @@ -0,0 +1,28 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > + > +#include <console/console.h> > +#include <device/device.h> > +#include <device/pci.h> > +#include <device/pci_ids.h> > +#include "chip.h" > + > +struct chip_operations mainboard_ops = { > + CHIP_NAME("ASUS M2V Mainboard") > +}; > diff -Naru src/mainboard/asus/m2v.none/mptable.c > src/mainboard/asus/m2v/mptable.c > --- src/mainboard/asus/m2v.none/mptable.c 1970-01-01 > 01:00:00.000000000 +0100 > +++ src/mainboard/asus/m2v/mptable.c 2010-10-20 19:57:57.000000000 +0200 > @@ -0,0 +1,146 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > + > +#include <string.h> > +#include <stdint.h> > +#include <arch/smp/mpspec.h> > +#include <arch/ioapic.h> > +#include "southbridge/via/vt8237r/vt8237r.h" > +#include "southbridge/via/k8t890/k8t890.h" > + > +static void *smp_write_config_table(void *v) > +{ > + static const char sig[4] = "PCMP"; > + static const char oem[8] = "COREBOOT"; > + static const char productid[12] = "M2V "; > + struct mp_config_table *mc; > + int bus_isa = 42; > + > + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); > + memset(mc, 0, sizeof(*mc)); > + > + memcpy(mc->mpc_signature, sig, sizeof(sig)); > + mc->mpc_length = sizeof(*mc); /* Initially just the header. */ > + mc->mpc_spec = 0x04; > + mc->mpc_checksum = 0; /* Not yet computed. */ > + memcpy(mc->mpc_oem, oem, sizeof(oem)); > + memcpy(mc->mpc_productid, productid, sizeof(productid)); > + mc->mpc_oemptr = 0; > + mc->mpc_oemsize = 0; > + mc->mpc_entry_count = 0; /* No entries yet. */ > + mc->mpc_lapic = LAPIC_ADDR; > + mc->mpe_length = 0; > + mc->mpe_checksum = 0; > + mc->reserved = 0; > + > + smp_write_processors(mc); > + > + > + /* Bus: Bus ID Type */ > + smp_write_bus(mc, 0, "PCI "); > + smp_write_bus(mc, 1, "PCI "); > + smp_write_bus(mc, 2, "PCI "); > + smp_write_bus(mc, 3, "PCI "); > + smp_write_bus(mc, 4, "PCI "); > + smp_write_bus(mc, 5, "PCI "); > + smp_write_bus(mc, 6, "PCI "); > + smp_write_bus(mc, bus_isa, "ISA "); > + > + /* I/O APICs: APIC ID Version State Address */ > + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); > + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); > + > + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); > + > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, > VT8237R_APIC_ID, 0x10); //IRQ16 > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, > VT8237R_APIC_ID, 0x11); //IRQ17 > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, > VT8237R_APIC_ID, 0x12); //IRQ18 > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, > VT8237R_APIC_ID, 0x13); //IRQ19 > + > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, > VT8237R_APIC_ID, 0x11); //IRQ17 > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, > VT8237R_APIC_ID, 0x12); //IRQ18 > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, > VT8237R_APIC_ID, 0x13); //IRQ19 > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, > VT8237R_APIC_ID, 0x10); //IRQ16 > + > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, > VT8237R_APIC_ID, 0x12); //IRQ18 > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, > VT8237R_APIC_ID, 0x13); //IRQ19 > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, > VT8237R_APIC_ID, 0x10); //IRQ16 > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, > VT8237R_APIC_ID, 0x11); //IRQ17 > + > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, > VT8237R_APIC_ID, 0x14); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, > VT8237R_APIC_ID, 0x14); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, > VT8237R_APIC_ID, 0x15); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, > VT8237R_APIC_ID, 0x15); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, > VT8237R_APIC_ID, 0x15); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, > VT8237R_APIC_ID, 0x16); > + > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, > K8T890_APIC_ID, 0x3); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, > K8T890_APIC_ID, 0x3); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, > K8T890_APIC_ID, 0x3); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, > K8T890_APIC_ID, 0x3); > + > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, > K8T890_APIC_ID, 0x7); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, > K8T890_APIC_ID, 0xb); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, > K8T890_APIC_ID, 0xf); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, > K8T890_APIC_ID, 0x13); > + > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, > K8T890_APIC_ID, 0x0); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, > K8T890_APIC_ID, 0x1); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, > K8T890_APIC_ID, 0x2); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, > K8T890_APIC_ID, 0x3); > + > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, > K8T890_APIC_ID, 0x4); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, > K8T890_APIC_ID, 0x5); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, > K8T890_APIC_ID, 0x6); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, > K8T890_APIC_ID, 0x7); > + > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, > K8T890_APIC_ID, 0x8); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, > K8T890_APIC_ID, 0x9); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, > K8T890_APIC_ID, 0xa); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, > K8T890_APIC_ID, 0xb); > + > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, > K8T890_APIC_ID, 0xc); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, > K8T890_APIC_ID, 0xd); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, > K8T890_APIC_ID, 0xe); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, > K8T890_APIC_ID, 0xf); > + > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, > K8T890_APIC_ID, 0x10); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, > K8T890_APIC_ID, 0x11); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, > K8T890_APIC_ID, 0x12); > + smp_write_intsrc(mc, mp_INT, > MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, > K8T890_APIC_ID, 0x13); > + > + /* Local Ints: Type Polarity Trigger Bus ID IRQ > APIC ID PIN# */ > + smp_write_intsrc(mc, mp_ExtINT, > MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); > + smp_write_intsrc(mc, mp_NMI, > MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); > + /* There is no extension information... */ > + > + /* Compute the checksums. */ > + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), > + mc->mpe_length); > + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); > + > + return smp_next_mpe_entry(mc); > +} > + > +unsigned long write_smp_table(unsigned long addr) > +{ > + void *v; > + v = smp_write_floating_table(addr); > + return (unsigned long)smp_write_config_table(v); > +} > diff -Naru src/mainboard/asus/m2v.none/romstage_a8v-e_se.c > src/mainboard/asus/m2v/romstage_a8v-e_se.c > --- src/mainboard/asus/m2v.none/romstage_a8v-e_se.c 1970-01-01 > 01:00:00.000000000 +0100 > +++ src/mainboard/asus/m2v/romstage_a8v-e_se.c 2010-10-20 > 20:43:06.000000000 +0200 > @@ -0,0 +1,244 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Copyright (C) 2006 AMD > + * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) > + * Copyright (C) 2006 MSI > + * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) > + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > + > +unsigned int get_sbdn(unsigned bus); > + > +/* Used by raminit. */ > +#define QRANK_DIMM_SUPPORT 1 > + > +/* Used by init_cpus and fidvid */ > +#define SET_FIDVID 1 > + > +/* If we want to wait for core1 done before DQS training, set it to 0. */ > +#define SET_FIDVID_CORE0_ONLY 1 > + > +#include <stdint.h> > +#include <string.h> > +#include <device/pci_def.h> > +#include <arch/io.h> > +#include <device/pnp_def.h> > +#include <arch/romcc_io.h> > +#include <cpu/x86/lapic.h> > +#include <pc80/mc146818rtc.h> > +#include <console/console.h> > +#include <cpu/amd/model_fxx_rev.h> > +#include "northbridge/amd/amdk8/raminit.h" > +#include "cpu/amd/model_fxx/apic_timer.c" > +#include "lib/delay.c" > +#include "cpu/x86/lapic/boot_cpu.c" > +#include "northbridge/amd/amdk8/reset_test.c" > +#include "northbridge/amd/amdk8/early_ht.c" > +#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" > +#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" > +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! > */ > +#include "cpu/x86/mtrr/earlymtrr.c" > +#include "cpu/x86/bist.h" > +#include "northbridge/amd/amdk8/setup_resource_map.c" > + > +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) > +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED) > +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) > +#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC) > + > +static void memreset(int controllers, const struct mem_controller *ctrl) > +{ > +} > + > +static inline int spd_read_byte(unsigned device, unsigned address) > +{ > + return smbus_read_byte(device, address); > +} > + > +static void activate_spd_rom(const struct mem_controller *ctrl) > +{ > +} > + > +#include <reset.h> > +void soft_reset(void) > +{ > + uint8_t tmp; > + > + set_bios_reset(); > + print_debug("soft reset \n"); > + > + /* PCI reset */ > + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); > + tmp |= 0x01; > + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); > + > + while (1) { > + /* daisy daisy ... */ > + hlt(); > + } > +} > + > +// defines S3_NVRAM_EARLY: > +#include "southbridge/via/k8t890/k8t890_early_car.c" > + > +#include "northbridge/amd/amdk8/amdk8.h" > +#include "northbridge/amd/amdk8/incoherent_ht.c" > +#include "northbridge/amd/amdk8/coherent_ht.c" > +#include "northbridge/amd/amdk8/raminit.c" > +#include "lib/generic_sdram.c" > + > +#include "cpu/amd/dualcore/dualcore.c" > + > +#include "cpu/amd/car/post_cache_as_ram.c" > +#include "cpu/amd/model_fxx/init_cpus.c" > +#include "cpu/amd/model_fxx/fidvid.c" > +#include "northbridge/amd/amdk8/resourcemap.c" > + > +unsigned int get_sbdn(unsigned bus) > +{ > + device_t dev; > + > + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, > + PCI_DEVICE_ID_VIA_VT8237R_LPC), > bus); > + return (dev >> 15) & 0x1f; > +} > + > +static void sio_init(void) > +{ > + u8 reg; > + > + pnp_enter_ext_func_mode(SERIAL_DEV); > + /* We have 24MHz input. */ > + reg = pnp_read_config(SERIAL_DEV, 0x24); > + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); > + /* We have GPIO for KB/MS pin. */ > + reg = pnp_read_config(SERIAL_DEV, 0x2a); > + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); > + /* We have all RESTOUT and even some reserved bits, too. */ > + reg = pnp_read_config(SERIAL_DEV, 0x2c); > + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); > + pnp_exit_ext_func_mode(SERIAL_DEV); > + > + pnp_enter_ext_func_mode(ACPI_DEV); > + pnp_set_logical_device(ACPI_DEV); > + /* > + * Set the delay rising time from PWROK_LP to PWROK_ST to > + * 300 - 600ms, and 0 to vice versa. > + */ > + reg = pnp_read_config(ACPI_DEV, 0xe6); > + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); > + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ > + reg = pnp_read_config(ACPI_DEV, 0xe4); > + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); > + pnp_exit_ext_func_mode(ACPI_DEV); > + > + pnp_enter_ext_func_mode(GPIO_DEV); > + pnp_set_logical_device(GPIO_DEV); > + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset > voltage. */ > + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. > */ > + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ > + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ > + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output > 1=input */ > + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output > 1=input */ > + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ > + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 > 0100). */ > + pnp_exit_ext_func_mode(GPIO_DEV); > +} > + > +void cache_as_ram_main(unsigned long bist, unsigned long > cpu_init_detectedx) > +{ > + static const uint16_t spd_addr[] = { > + // Node 0 > + (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, > + (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, > + // Node 1 > + (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, > + (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, > + }; > + unsigned bsp_apicid = 0; > + int needs_reset = 0; > + struct sys_info *sysinfo = (struct sys_info > *)(CONFIG_DCACHE_RAM_BASE > + + CONFIG_DCACHE_RAM_SIZE - > CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); > + > + sio_init(); > + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); > + uart_init(); > + console_init(); > + enable_rom_decode(); > + > + print_info("now booting... fallback\n"); > + > + /* Is this a CPU only reset? Or is this a secondary CPU? */ > + if (!cpu_init_detectedx && boot_cpu()) { > + /* Nothing special needs to be done to find bus 0. */ > + /* Allow the HT devices to be found. */ > + enumerate_ht_chain(); > + } > + > + sio_init(); > + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); > + uart_init(); > + console_init(); > + enable_rom_decode(); > + > + print_info("now booting... real_main\n"); > + > + if (bist == 0) > + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); > + > + /* Halt if there was a built in self test failure. */ > + report_bist_failure(bist); > + > + setup_default_resource_map(); > + setup_coherent_ht_domain(); > + wait_all_core0_started(); > + > + print_info("now booting... Core0 started\n"); > + > +#if CONFIG_LOGICAL_CPUS==1 > + /* It is said that we should start core1 after all core0 launched. > */ > + start_other_cores(); > + wait_all_other_cores_started(bsp_apicid); > +#endif > + init_timer(); > + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. > */ > + > + needs_reset = optimize_link_coherent_ht(); > + needs_reset |= optimize_link_incoherent_ht(sysinfo); > + needs_reset |= k8t890_early_setup_ht(); > + > + if (needs_reset) { > + print_debug("ht reset -\n"); > + soft_reset(); > + } > + > + /* the HT settings needs to be OK, because link freq chnage may > cause HT disconnect */ > + enable_fid_change(); > + init_fidvid_bsp(bsp_apicid); > + > + /* Stop the APs so we can start them later in init. */ > + allow_all_aps_stop(bsp_apicid); > + > + /* It's the time to set ctrl now. */ > + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); > + > + enable_smbus(); > + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); > + post_cache_as_ram(); > +} > + > diff -Naru src/mainboard/asus/m2v.none/romstage.c > src/mainboard/asus/m2v/romstage.c > --- src/mainboard/asus/m2v.none/romstage.c 1970-01-01 > 01:00:00.000000000 +0100 > +++ src/mainboard/asus/m2v/romstage.c 2010-10-20 22:58:40.000000000 +0200 > @@ -0,0 +1,210 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Copyright (C) 2006 AMD > + * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) > + * Copyright (C) 2006 MSI > + * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) > + * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > + > +unsigned int get_sbdn(unsigned bus); > + > +/* Used by raminit. */ > +#define QRANK_DIMM_SUPPORT 1 > + > +/* Used by init_cpus and fidvid */ > +#define SET_FIDVID 1 > + > +/* If we want to wait for core1 done before DQS training, set it to 0. */ > +#define SET_FIDVID_CORE0_ONLY 1 > + > +#if CONFIG_K8_REV_F_SUPPORT == 1 > +#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 > +#endif > + > +#include <stdint.h> > +#include <string.h> > +#include <device/pci_def.h> > +#include <arch/io.h> > +#include <device/pnp_def.h> > +#include <arch/romcc_io.h> > +#include <cpu/amd/mtrr.h> > +#include <cpu/x86/lapic.h> > +#include <pc80/mc146818rtc.h> > +#include <console/console.h> > +#include <cpu/amd/model_fxx_rev.h> > +#include "northbridge/amd/amdk8/raminit.h" > +#include "cpu/amd/model_fxx/apic_timer.c" > +#include "lib/delay.c" > +#include "northbridge/amd/amdk8/reset_test.c" > +#include "northbridge/amd/amdk8/debug.c" > +#include "superio/ite/it8712f/it8712f_early_serial.c" > +#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" > +#include "cpu/x86/mtrr/earlymtrr.c" > +#include "cpu/x86/bist.h" > +#include "northbridge/amd/amdk8/setup_resource_map.c" > + > +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) > +#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) > + > +static void memreset(int controllers, const struct mem_controller *ctrl) > +{ > +} > + > +static inline int spd_read_byte(unsigned device, unsigned address) > +{ > + return smbus_read_byte(device, address); > +} > + > +static void activate_spd_rom(const struct mem_controller *ctrl) > +{ > +} > + > +// defines S3_NVRAM_EARLY: > +#include "southbridge/via/k8t890/k8t890_early_car.c" > + > +#include "northbridge/amd/amdk8/amdk8.h" > +#include "northbridge/amd/amdk8/incoherent_ht.c" > +#include "northbridge/amd/amdk8/coherent_ht.c" > +#include "northbridge/amd/amdk8/raminit_f.c" > +#include "lib/generic_sdram.c" > + > +#include "cpu/amd/dualcore/dualcore.c" > + > +#include "cpu/amd/car/post_cache_as_ram.c" > +#include "cpu/amd/model_fxx/init_cpus.c" > + > +#define SB_VFSMAF 0 > + > +/* this function might fail on some K8 CPUs with errata #181 */ > +static void ldtstop_sb(void) > +{ > + print_debug("toggle LDTSTP#\n"); > + u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c); > + reg = reg ^ (1 << 0); > + outb(reg, VT8237R_ACPI_IO_BASE + 0x5c); > + reg = inb(VT8237R_ACPI_IO_BASE + 0x15); > + print_debug("done\n"); > +} > + > +#include "cpu/amd/model_fxx/fidvid.c" > +#include "northbridge/amd/amdk8/resourcemap.c" > + > +void soft_reset(void) > +{ > + uint8_t tmp; > + > + set_bios_reset(); > + print_debug("soft reset \n"); > + > + /* PCI reset */ > + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); > + tmp |= 0x01; > + /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ > + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); > + > + while (1) { > + /* daisy daisy ... */ > + hlt(); > + } > +} > + > +unsigned int get_sbdn(unsigned bus) > +{ > + device_t dev; > + > + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, > + PCI_DEVICE_ID_VIA_VT8237R_LPC), > bus); > + return (dev >> 15) & 0x1f; > +} > + > +void cache_as_ram_main(unsigned long bist, unsigned long > cpu_init_detectedx) > +{ > + static const uint16_t spd_addr[] = { > + // Node 0 > + (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, > + (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, > + // Node 1 > + (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, > + (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, > + }; > + unsigned bsp_apicid = 0; > + int needs_reset = 0; > + struct sys_info *sysinfo = > + (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + > CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); > + > + it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); > + it8712f_kill_watchdog(); > + it8712f_enable_3vsbsw(); > + uart_init(); > + console_init(); > + enable_rom_decode(); > + > + printk(BIOS_INFO, "now booting... \n"); > + > + if (bist == 0) > + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); > + > + /* Halt if there was a built in self test failure. */ > + report_bist_failure(bist); > + setup_default_resource_map(); > + setup_coherent_ht_domain(); > + wait_all_core0_started(); > + > + printk(BIOS_INFO, "now booting... All core 0 started\n"); > + > +#if CONFIG_LOGICAL_CPUS==1 > + /* It is said that we should start core1 after all core0 launched. > */ > + start_other_cores(); > + wait_all_other_cores_started(bsp_apicid); > +#endif > + init_timer(); > + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. > */ > + > + needs_reset = optimize_link_coherent_ht(); > + print_debug_hex8(needs_reset); > + needs_reset |= optimize_link_incoherent_ht(sysinfo); > + print_debug_hex8(needs_reset); > + needs_reset |= k8t890_early_setup_ht(); > + print_debug_hex8(needs_reset); > + > + if (needs_reset) { > + printk(BIOS_DEBUG, "ht reset -\n"); > + soft_reset(); > + printk(BIOS_DEBUG, "FAILED!\n"); > + } > + > + /* the HT settings needs to be OK, because link freq chnage may > cause HT disconnect */ > + /* allow LDT STOP asserts */ > + vt8237_sb_enable_fid_vid(); > + > + enable_fid_change(); > + print_debug("after enable_fid_change\n"); > + > + init_fidvid_bsp(bsp_apicid); > + > + /* Stop the APs so we can start them later in init. */ > + allow_all_aps_stop(bsp_apicid); > + > + /* It's the time to set ctrl now. */ > + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); > + enable_smbus(); > + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); > + post_cache_as_ram(); > +} > + > diff -Naru src/mainboard/asus/m2v.none/romstage_m2v-mx_se.c > src/mainboard/asus/m2v/romstage_m2v-mx_se.c > --- src/mainboard/asus/m2v.none/romstage_m2v-mx_se.c 1970-01-01 > 01:00:00.000000000 +0100 > +++ src/mainboard/asus/m2v/romstage_m2v-mx_se.c 2010-10-20 > 20:43:15.000000000 +0200 > @@ -0,0 +1,213 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Copyright (C) 2006 AMD > + * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) > + * Copyright (C) 2006 MSI > + * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) > + * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > + > +unsigned int get_sbdn(unsigned bus); > + > +/* Used by raminit. */ > +#define QRANK_DIMM_SUPPORT 1 > + > +/* Used by init_cpus and fidvid */ > +#define SET_FIDVID 1 > + > +/* If we want to wait for core1 done before DQS training, set it to 0. */ > +#define SET_FIDVID_CORE0_ONLY 1 > + > +#if CONFIG_K8_REV_F_SUPPORT == 1 > +#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 > +#endif > + > +#include <stdint.h> > +#include <string.h> > +#include <device/pci_def.h> > +#include <arch/io.h> > +#include <device/pnp_def.h> > +#include <arch/romcc_io.h> > +#include <cpu/amd/mtrr.h> > +#include <cpu/x86/lapic.h> > +#include <pc80/mc146818rtc.h> > +#include <console/console.h> > +#include <cpu/amd/model_fxx_rev.h> > +#include "northbridge/amd/amdk8/raminit.h" > +#include "cpu/amd/model_fxx/apic_timer.c" > +#include "lib/delay.c" > +#include "northbridge/amd/amdk8/reset_test.c" > +#include "northbridge/amd/amdk8/debug.c" > +#include "superio/ite/it8712f/it8712f_early_serial.c" > +#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" > +#include "cpu/x86/mtrr/earlymtrr.c" > +#include "cpu/x86/bist.h" > +#include "northbridge/amd/amdk8/setup_resource_map.c" > + > +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) > +#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) > + > +static void memreset(int controllers, const struct mem_controller *ctrl) > +{ > +} > + > +static inline int spd_read_byte(unsigned device, unsigned address) > +{ > + return smbus_read_byte(device, address); > +} > + > +static void activate_spd_rom(const struct mem_controller *ctrl) > +{ > +} > + > +// defines S3_NVRAM_EARLY: > +#include "southbridge/via/k8t890/k8t890_early_car.c" > + > +#include "northbridge/amd/amdk8/amdk8.h" > +#include "northbridge/amd/amdk8/incoherent_ht.c" > +#include "northbridge/amd/amdk8/coherent_ht.c" > +#include "northbridge/amd/amdk8/raminit_f.c" > +#include "lib/generic_sdram.c" > + > +#include "cpu/amd/dualcore/dualcore.c" > + > +#include "cpu/amd/car/post_cache_as_ram.c" > +#include "cpu/amd/model_fxx/init_cpus.c" > + > +#define SB_VFSMAF 0 > + > +/* this function might fail on some K8 CPUs with errata #181 */ > +static void ldtstop_sb(void) > +{ > + print_debug("toggle LDTSTP#\n"); > + u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c); > + reg = reg ^ (1 << 0); > + outb(reg, VT8237R_ACPI_IO_BASE + 0x5c); > + reg = inb(VT8237R_ACPI_IO_BASE + 0x15); > + print_debug("done\n"); > +} > + > +#include "cpu/amd/model_fxx/fidvid.c" > +#include "northbridge/amd/amdk8/resourcemap.c" > + > +void soft_reset(void) > +{ > + uint8_t tmp; > + > + set_bios_reset(); > + print_debug("soft reset \n"); > + > + /* PCI reset */ > + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); > + tmp |= 0x01; > + /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ > + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); > + > + while (1) { > + /* daisy daisy ... */ > + hlt(); > + } > +} > + > +unsigned int get_sbdn(unsigned bus) > +{ > + device_t dev; > + > + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, > + PCI_DEVICE_ID_VIA_VT8237R_LPC), > bus); > + return (dev >> 15) & 0x1f; > +} > + > +void cache_as_ram_main(unsigned long bist, unsigned long > cpu_init_detectedx) > +{ > + static const uint16_t spd_addr[] = { > + // Node 0 > + (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, > + (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, > + // Node 1 > + (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, > + (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, > + }; > + unsigned bsp_apicid = 0; > + int needs_reset = 0; > + struct sys_info *sysinfo = > + (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + > CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); > + > + it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); > + it8712f_kill_watchdog(); > + it8712f_enable_3vsbsw(); > + uart_init(); > + console_init(); > + enable_rom_decode(); > + > + printk(BIOS_INFO, "now booting... \n"); > + > + if (bist == 0) > + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); > + > + /* Halt if there was a built in self test failure. */ > + report_bist_failure(bist); > + setup_default_resource_map(); > + setup_coherent_ht_domain(); > + wait_all_core0_started(); > + > + printk(BIOS_INFO, "now booting... All core 0 started\n"); > + > +#if CONFIG_LOGICAL_CPUS==1 > + /* It is said that we should start core1 after all core0 launched. > */ > + start_other_cores(); > + wait_all_other_cores_started(bsp_apicid); > +#endif > + init_timer(); > + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. > */ > + > + needs_reset = optimize_link_coherent_ht(); > + print_debug_hex8(needs_reset); > + needs_reset |= optimize_link_incoherent_ht(sysinfo); > + print_debug_hex8(needs_reset); > + needs_reset |= k8t890_early_setup_ht(); > + print_debug_hex8(needs_reset); > + > + vt8237_early_network_init(NULL); > + vt8237_early_spi_init(); > + > + if (needs_reset) { > + printk(BIOS_DEBUG, "ht reset -\n"); > + soft_reset(); > + printk(BIOS_DEBUG, "FAILED!\n"); > + } > + > + /* the HT settings needs to be OK, because link freq chnage may > cause HT disconnect */ > + /* allow LDT STOP asserts */ > + vt8237_sb_enable_fid_vid(); > + > + enable_fid_change(); > + print_debug("after enable_fid_change\n"); > + > + init_fidvid_bsp(bsp_apicid); > + > + /* Stop the APs so we can start them later in init. */ > + allow_all_aps_stop(bsp_apicid); > + > + /* It's the time to set ctrl now. */ > + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); > + enable_smbus(); > + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); > + post_cache_as_ram(); > +} > + > > > > -- > Tobias PGP: > http://8ef7ddba.uguu.de > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >
The 0:2.0 is the PCIe 16x right? Maybe try without VGA first? Can you track down where it hangs exactly? Thanks, Rudolf
Rudolf Marek wrote: > The 0:2.0 is the PCIe 16x right? > > Maybe try without VGA first? Can you track down where it hangs exactly? I tried both with and without a device in the peg slot (only network card though). BTW, I have different K8T890 pci ids (K8T890CF), so maybe some part fo the setup there has to be different?
Tobias Diedrich wrote: > Rudolf Marek wrote: > > The 0:2.0 is the PCIe 16x right? > > > > Maybe try without VGA first? Can you track down where it hangs exactly? > > I tried both with and without a device in the peg slot (only network > card though). > > BTW, I have different K8T890 pci ids (K8T890CF), so maybe some part > fo the setup there has to be different? I got it past probing by copying cfg space values from the orig bios in k8t890_pcie.c Now it hangs in bridge decode enable: Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/00 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:00.0 cmd <- 00 PCI: 00:00.1 cmd <- 06 PCI: 00:00.2 cmd <- 06 PCI: 00:00.3 cmd <- 06 PCI: 00:00.4 cmd <- 06 PCI: 00:00.5 cmd <- 06 PCI: 00:00.6 cmd <- 06 PCI: 00:00.7 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 0017 PCI: 00:01.0 cmd <- 04 PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 00 PCI: 00:03.0 bridge ctrl <- 0003 PCI: 00:03.0 cmd <- 07 [hang] 00:03.0 is one of the onboard pcie devices.
]PCI: 00:01.0 bridge ctrl <- 0017 ]PCI: 00:01.0 cmd <- 04 ]PCI: 00:02.0 bridge ctrl <- 0003 ]PCI: 00:02.0 cmd <- 00 ]PCI: 00:03.0 bridge ctrl <- 0003 ]PCI: 00:03.0 cmd <- 07 ][hang] ] ]00:03.0 is one of the onboard pcie devices. ] ]-- ]Tobias PGP: http://8ef7ddba.uguu.de The write of 07 enables memory bars, I/O bars, and bus master for that device. You could try to dump the config space for that device to see if memory and I/O bars are reasonable. Knowing MTRRs and TOM would let you confirm the memory bars point to UC-IO. Thanks, Scott
Scott Duplichan wrote: > ]PCI: 00:01.0 bridge ctrl <- 0017 > ]PCI: 00:01.0 cmd <- 04 > ]PCI: 00:02.0 bridge ctrl <- 0003 > ]PCI: 00:02.0 cmd <- 00 > ]PCI: 00:03.0 bridge ctrl <- 0003 > ]PCI: 00:03.0 cmd <- 07 > ][hang] > ] > ]00:03.0 is one of the onboard pcie devices. > ] > ]-- > ]Tobias PGP: http://8ef7ddba.uguu.de > > The write of 07 enables memory bars, I/O bars, and bus master > for that device. You could try to dump the config space for that > device to see if memory and I/O bars are reasonable. Knowing > MTRRs and TOM would let you confirm the memory bars point to UC-IO. Ok, it's a problem with the resource allocator. It's allocating io 0x000-0xfff to this bridge, and the existing 'avoid legacy ports' checks don't seem to catch this. |Done setting resources. |Show resources in subtree (Root Device)...After assigning values. |[...] | PCI: 00:03.0 child on link 0 PCI: 03:00.0 | PCI: 00:03.0 resource base 0 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c | PCI: 00:03.0 resource base fecbffff size 0 align 20 gran 20 limit fecbffff flags 60081202 in | PCI: 00:03.0 resource base f0000000 size 100000 align 20 gran 20 limit fecbffff flags 600802 | PCI: 03:00.0 | PCI: 03:00.0 resource base 10 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 | PCI: 03:00.0 resource base 20 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 | PCI: 03:00.0 resource base 18 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 | PCI: 03:00.0 resource base 24 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c | PCI: 03:00.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 | PCI: 03:00.0 resource base f0000000 size 400 align 10 gran 10 limit fecbffff flags 60000200 | PCI: 00:03.1 child on link 0 PCI: 04:00.0 | PCI: 00:03.1 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1 The devices/device.c has two checks to defend legacy ports in compute_resources and allocate_resources: | if (resource->flags & IORESOURCE_IO) { | /* Don't allow potential aliases over the legacy PCI | * expansion card addresses. The legacy PCI decodes | * only 10 bits, uses 0x100 - 0x3ff. Therefore, only | * 0x00 - 0xff can be used out of each 0x400 block of | * I/O space. | */ | if ((base & 0x300) != 0) { | base = (base & ~0x3ff) + 0x400; | } | /* Don't allow allocations in the VGA I/O range. | * PCI has special cases for that. | */ | else if ((base >= 0x3b0) && (base <= 0x3df)) { | base = 0x3e0; | } | } This doesn't prevent the bridge from getting allocated 0x0000-0x0fff. I added | /* exclude 0x0000 - 0x0400 legacy range */ | if (base <= 0x400) { | base = 0x400; | } and now it's booting and handing off to seabios (but video card init doesn't seem to work). |Done setting resources. |Show resources in subtree (Root Device)...After assigning values. |[...] | PCI: 00:03.0 child on link 0 PCI: 03:00.0 | PCI: 00:03.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1 | PCI: 00:03.0 resource base fecbffff size 0 align 20 gran 20 limit fecbffff flags 60081202 in | PCI: 00:03.0 resource base f0000000 size 100000 align 20 gran 20 limit fecbffff flags 600802 | PCI: 03:00.0 | PCI: 03:00.0 resource base 1010 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 | PCI: 03:00.0 resource base 1020 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 | PCI: 03:00.0 resource base 1018 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 | PCI: 03:00.0 resource base 1024 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c | PCI: 03:00.0 resource base 1000 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 | PCI: 03:00.0 resource base f0000000 size 400 align 10 gran 10 limit fecbffff flags 60000200 | PCI: 00:03.1 child on link 0 PCI: 04:00.0 | PCI: 00:03.1 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1 | PCI: 00:03.1 resource base fecbffff size 0 align 20 gran 20 limit fecbffff flags 60081202 in | PCI: 00:03.1 resource base f0100000 size 100000 align 20 gran 20 limit fecbffff flags 600802 |[...] |Start bios (version pre-0.6.2-20101020_194120-nukunuku) |Found mainboard ASUS M2V |Found CBFS header at 0xfffffc6e |Ram Size=0xdfff0000 (0x0000000100000000 high) |Relocating init from 0x000e9330 to 0xdffd6880 (size 38496) |CPU Mhz=1001 |Found 1 cpu(s) max supported 1 cpu(s) |Copying MPTABLE from 0xdfff0400/dfff0410 to 0x000fda50 |SMBIOS ptr=0x000fda30 table=0xdffefed0 |Scan for VGA option rom |EHCI init on dev 00:10.4 (regs=0xf0300010) |Found 0 lpt ports |Found 2 serial ports |ATA controller 0 at 1f0/3f4/0 (irq 14 dev 79) |ATA controller 1 at 170/374/0 (irq 15 dev 79) |ATA controller 2 at 1010/1020/0 (irq 0 dev 300) |ATA controller 3 at 1018/1024/0 (irq 0 dev 300) |ata1-1: Pioneer DVD-ROM ATAPIModel DVD-106S 0122 ATAPI-5 DVD/CD |PS2 keyboard initialized |All threads complete. |Scan for option roms |Press F12 for boot menu.
In case someone finds this in the ml archive by googling:
The problem was that I had missed adding a pci id for the lpc/isa
bridge, which reserves ports 0x0000-0x0fff:
static void vt8237r_read_resources(device_t dev)
{
[...]
res = new_resource(dev, 1);
res->base = 0x0UL;
res->size = 0x1000UL;
res->limit = 0xffffUL;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
Tobias Diedrich wrote:
> Scott Duplichan wrote:
> > ]PCI: 00:01.0 bridge ctrl <- 0017
> > ]PCI: 00:01.0 cmd <- 04
> > ]PCI: 00:02.0 bridge ctrl <- 0003
> > ]PCI: 00:02.0 cmd <- 00
> > ]PCI: 00:03.0 bridge ctrl <- 0003
> > ]PCI: 00:03.0 cmd <- 07
> > ][hang]
> > ]
> > ]00:03.0 is one of the onboard pcie devices.
> > ]
> > ]--
> > ]Tobias PGP: http://8ef7ddba.uguu.de
> >
> > The write of 07 enables memory bars, I/O bars, and bus master
> > for that device. You could try to dump the config space for that
> > device to see if memory and I/O bars are reasonable. Knowing
> > MTRRs and TOM would let you confirm the memory bars point to UC-IO.
>
> Ok, it's a problem with the resource allocator.
> It's allocating io 0x000-0xfff to this bridge, and the existing
> 'avoid legacy ports' checks don't seem to catch this.
>
> |Done setting resources.
> |Show resources in subtree (Root Device)...After assigning values.
> |[...]
> | PCI: 00:03.0 child on link 0 PCI: 03:00.0
> | PCI: 00:03.0 resource base 0 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
> | PCI: 00:03.0 resource base fecbffff size 0 align 20 gran 20 limit fecbffff flags 60081202 in
> | PCI: 00:03.0 resource base f0000000 size 100000 align 20 gran 20 limit fecbffff flags 600802
> | PCI: 03:00.0
> | PCI: 03:00.0 resource base 10 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
> | PCI: 03:00.0 resource base 20 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
> | PCI: 03:00.0 resource base 18 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
> | PCI: 03:00.0 resource base 24 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
> | PCI: 03:00.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
> | PCI: 03:00.0 resource base f0000000 size 400 align 10 gran 10 limit fecbffff flags 60000200
> | PCI: 00:03.1 child on link 0 PCI: 04:00.0
> | PCI: 00:03.1 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1
>
> The devices/device.c has two checks to defend legacy ports in
> compute_resources and allocate_resources:
>
> | if (resource->flags & IORESOURCE_IO) {
> | /* Don't allow potential aliases over the legacy PCI
> | * expansion card addresses. The legacy PCI decodes
> | * only 10 bits, uses 0x100 - 0x3ff. Therefore, only
> | * 0x00 - 0xff can be used out of each 0x400 block of
> | * I/O space.
> | */
> | if ((base & 0x300) != 0) {
> | base = (base & ~0x3ff) + 0x400;
> | }
> | /* Don't allow allocations in the VGA I/O range.
> | * PCI has special cases for that.
> | */
> | else if ((base >= 0x3b0) && (base <= 0x3df)) {
> | base = 0x3e0;
> | }
> | }
>
> This doesn't prevent the bridge from getting allocated 0x0000-0x0fff.
>
> I added
> | /* exclude 0x0000 - 0x0400 legacy range */
> | if (base <= 0x400) {
> | base = 0x400;
> | }
>
> and now it's booting and handing off to seabios (but video card init
> doesn't seem to work).
>
> |Done setting resources.
> |Show resources in subtree (Root Device)...After assigning values.
> |[...]
> | PCI: 00:03.0 child on link 0 PCI: 03:00.0
> | PCI: 00:03.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1
> | PCI: 00:03.0 resource base fecbffff size 0 align 20 gran 20 limit fecbffff flags 60081202 in
> | PCI: 00:03.0 resource base f0000000 size 100000 align 20 gran 20 limit fecbffff flags 600802
> | PCI: 03:00.0
> | PCI: 03:00.0 resource base 1010 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
> | PCI: 03:00.0 resource base 1020 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
> | PCI: 03:00.0 resource base 1018 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
> | PCI: 03:00.0 resource base 1024 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
> | PCI: 03:00.0 resource base 1000 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
> | PCI: 03:00.0 resource base f0000000 size 400 align 10 gran 10 limit fecbffff flags 60000200
> | PCI: 00:03.1 child on link 0 PCI: 04:00.0
> | PCI: 00:03.1 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1
> | PCI: 00:03.1 resource base fecbffff size 0 align 20 gran 20 limit fecbffff flags 60081202 in
> | PCI: 00:03.1 resource base f0100000 size 100000 align 20 gran 20 limit fecbffff flags 600802
> |[...]
> |Start bios (version pre-0.6.2-20101020_194120-nukunuku)
> |Found mainboard ASUS M2V
> |Found CBFS header at 0xfffffc6e
> |Ram Size=0xdfff0000 (0x0000000100000000 high)
> |Relocating init from 0x000e9330 to 0xdffd6880 (size 38496)
> |CPU Mhz=1001
> |Found 1 cpu(s) max supported 1 cpu(s)
> |Copying MPTABLE from 0xdfff0400/dfff0410 to 0x000fda50
> |SMBIOS ptr=0x000fda30 table=0xdffefed0
> |Scan for VGA option rom
> |EHCI init on dev 00:10.4 (regs=0xf0300010)
> |Found 0 lpt ports
> |Found 2 serial ports
> |ATA controller 0 at 1f0/3f4/0 (irq 14 dev 79)
> |ATA controller 1 at 170/374/0 (irq 15 dev 79)
> |ATA controller 2 at 1010/1020/0 (irq 0 dev 300)
> |ATA controller 3 at 1018/1024/0 (irq 0 dev 300)
> |ata1-1: Pioneer DVD-ROM ATAPIModel DVD-106S 0122 ATAPI-5 DVD/CD
> |PS2 keyboard initialized
> |All threads complete.
> |Scan for option roms
> |Press F12 for boot menu.
>
> --
> Tobias PGP: http://8ef7ddba.uguu.de
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
Patch
Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r_early_smbus.c (revision 5976) +++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c (working copy) @@ -142,6 +142,7 @@ device_t dev; int loops; + print_debug("enable_smbus()\n"); /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); @@ -149,8 +150,13 @@ /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - if (dev == PCI_DEV_INVALID) - die("Power management controller not found\n"); + if (dev == PCI_DEV_INVALID) { + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); + if (dev == PCI_DEV_INVALID) + die("Power management controller not found\n"); + } } /* Make sure the RTC power well is up before touching smbus. */ @@ -242,15 +248,20 @@ if (dev == PCI_DEV_INVALID) { /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); + } + if (dev == PCI_DEV_INVALID) { + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - if (dev == PCI_DEV_INVALID) - return; devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237_VLINK), 0); - if (devctl == PCI_DEV_INVALID) + if (devctl == PCI_DEV_INVALID) { + print_err("vt8237_sb_enable_fid_vid() failed\n"); return; + } /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); @@ -297,7 +308,7 @@ if (dev == PCI_DEV_INVALID) { /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); + PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); if (dev == PCI_DEV_INVALID) return; } @@ -321,7 +332,7 @@ if (dev == PCI_DEV_INVALID) { /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); + PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); if (dev == PCI_DEV_INVALID) die("Power management controller not found\n"); } Index: src/include/device/pci_ids.h =================================================================== --- src/include/device/pci_ids.h (revision 5976) +++ src/include/device/pci_ids.h (working copy) @@ -1219,6 +1219,7 @@ #define PCI_DEVICE_ID_VIA_K8T890CE_BR 0xb188 #define PCI_DEVICE_ID_VIA_VT6420_SATA 0x3149 #define PCI_DEVICE_ID_VIA_VT8237R_LPC 0x3227 +#define PCI_DEVICE_ID_VIA_VT8237A_LPC 0x3337 #define PCI_DEVICE_ID_VIA_VT8237S_LPC 0x3372 #define PCI_DEVICE_ID_VIA_VT8237_SATA 0x5372 #define PCI_DEVICE_ID_VIA_VT8237_VLINK 0x287e Index: src/mainboard/asus/Kconfig =================================================================== --- src/mainboard/asus/Kconfig (revision 5976) +++ src/mainboard/asus/Kconfig (working copy) @@ -25,6 +25,8 @@ bool "A8N-E" config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" +config BOARD_ASUS_M2V + bool "M2V" config BOARD_ASUS_M2V_MX_SE bool "M2V-MX SE" config BOARD_ASUS_M4A785M @@ -50,6 +52,7 @@ source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" +source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" source "src/mainboard/asus/m4a785-m/Kconfig" source "src/mainboard/asus/mew-am/Kconfig" diff -Naru src/mainboard/asus/m2v.none/acpi_tables.c src/mainboard/asus/m2v/acpi_tables.c --- src/mainboard/asus/m2v.none/acpi_tables.c 1970-01-01 01:00:00.000000000 +0100 +++ src/mainboard/asus/m2v/acpi_tables.c 2010-10-20 19:17:51.000000000 +0200 @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer <stepan@openbios.org>. + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org> + * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff -Naru src/mainboard/asus/m2v.none/chip.h src/mainboard/asus/m2v/chip.h --- src/mainboard/asus/m2v.none/chip.h 1970-01-01 01:00:00.000000000 +0100 +++ src/mainboard/asus/m2v/chip.h 2010-10-20 19:17:51.000000000 +0200 @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff -Naru src/mainboard/asus/m2v.none/cmos.layout src/mainboard/asus/m2v/cmos.layout --- src/mainboard/asus/m2v.none/cmos.layout 1970-01-01 01:00:00.000000000 +0100 +++ src/mainboard/asus/m2v/cmos.layout 2010-10-20 19:17:51.000000000 +0200 @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff -Naru src/mainboard/asus/m2v.none/devicetree.cb src/mainboard/asus/m2v/devicetree.cb --- src/mainboard/asus/m2v.none/devicetree.cb 1970-01-01 01:00:00.000000000 +0100 +++ src/mainboard/asus/m2v/devicetree.cb 2010-10-21 01:50:56.000000000 +0200 @@ -0,0 +1,75 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_AM2 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0xc0" # Enable SB functions + register "fn_ctrl_hi" = "0x0d" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/ite/it8712f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 0x00 + end + device pnp 2e.5 off end # PS/2 keyboard + device pnp 2e.6 off end # PS/2 mouse + device pnp 2e.7 off end # GPIO config + device pnp 2e.8 off end # Midi port + device pnp 2e.9 off end # Game port + device pnp 2e.a off end # IR + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff -Naru src/mainboard/asus/m2v.none/dsdt.asl src/mainboard/asus/m2v/dsdt.asl --- src/mainboard/asus/m2v.none/dsdt.asl 1970-01-01 01:00:00.000000000 +0100 +++ src/mainboard/asus/m2v/dsdt.asl 2010-10-20 19:17:51.000000000 +0200 @@ -0,0 +1,211 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com> + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +{ + /* Define the main processor.*/ + Scope (\_PR) + { + Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {} + Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {} + } + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + /* PCI Routing Table */ + /* aaa */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + } + } +} diff -Naru src/mainboard/asus/m2v.none/Kconfig src/mainboard/asus/m2v/Kconfig --- src/mainboard/asus/m2v.none/Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ src/mainboard/asus/m2v/Kconfig 2010-10-20 22:52:31.000000000 +0200 @@ -0,0 +1,79 @@ +if BOARD_ASUS_M2V + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_AM2 + select DIMM_DDR2 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_ITE_IT8712F + select CACHE_AS_RAM + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select TINY_BOOTBLOCK +# select HAVE_MAINBOARD_RESOURCES + +config MAINBOARD_DIR + string + default asus/m2v + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "M2V" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1043 + +endif # BOARD_ASUS_M2V diff -Naru src/mainboard/asus/m2v.none/mainboard.c src/mainboard/asus/m2v/mainboard.c --- src/mainboard/asus/m2v.none/mainboard.c 1970-01-01 01:00:00.000000000 +0100 +++ src/mainboard/asus/m2v/mainboard.c 2010-10-20 19:57:44.000000000 +0200 @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS M2V Mainboard") +}; diff -Naru src/mainboard/asus/m2v.none/mptable.c src/mainboard/asus/m2v/mptable.c --- src/mainboard/asus/m2v.none/mptable.c 1970-01-01 01:00:00.000000000 +0100 +++ src/mainboard/asus/m2v/mptable.c 2010-10-20 19:57:57.000000000 +0200 @@ -0,0 +1,146 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <stdint.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "COREBOOT"; + static const char productid[12] = "M2V "; + struct mp_config_table *mc; + int bus_isa = 42; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* Initially just the header. */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* Not yet computed. */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet. */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + + /* Bus: Bus ID Type */ + smp_write_bus(mc, 0, "PCI "); + smp_write_bus(mc, 1, "PCI "); + smp_write_bus(mc, 2, "PCI "); + smp_write_bus(mc, 3, "PCI "); + smp_write_bus(mc, 4, "PCI "); + smp_write_bus(mc, 5, "PCI "); + smp_write_bus(mc, 6, "PCI "); + smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums. */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), + mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} diff -Naru src/mainboard/asus/m2v.none/romstage_a8v-e_se.c src/mainboard/asus/m2v/romstage_a8v-e_se.c --- src/mainboard/asus/m2v.none/romstage_a8v-e_se.c 1970-01-01 01:00:00.000000000 +0100 +++ src/mainboard/asus/m2v/romstage_a8v-e_se.c 2010-10-20 20:43:06.000000000 +0200 @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +/* Used by raminit. */ +#define QRANK_DIMM_SUPPORT 1 + +/* Used by init_cpus and fidvid */ +#define SET_FIDVID 1 + +/* If we want to wait for core1 done before DQS training, set it to 0. */ +#define SET_FIDVID_CORE0_ONLY 1 + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" +#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC) + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +static void activate_spd_rom(const struct mem_controller *ctrl) +{ +} + +#include <reset.h> +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +// defines S3_NVRAM_EARLY: +#include "southbridge/via/k8t890/k8t890_early_car.c" + +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" + +#include "cpu/amd/dualcore/dualcore.c" + +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, + (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, + // Node 1 + (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, + (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + enable_rom_decode(); + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} + diff -Naru src/mainboard/asus/m2v.none/romstage.c src/mainboard/asus/m2v/romstage.c --- src/mainboard/asus/m2v.none/romstage.c 1970-01-01 01:00:00.000000000 +0100 +++ src/mainboard/asus/m2v/romstage.c 2010-10-20 22:58:40.000000000 +0200 @@ -0,0 +1,210 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) + * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +/* Used by raminit. */ +#define QRANK_DIMM_SUPPORT 1 + +/* Used by init_cpus and fidvid */ +#define SET_FIDVID 1 + +/* If we want to wait for core1 done before DQS training, set it to 0. */ +#define SET_FIDVID_CORE0_ONLY 1 + +#if CONFIG_K8_REV_F_SUPPORT == 1 +#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 +#endif + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/ite/it8712f/it8712f_early_serial.c" +#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +static void activate_spd_rom(const struct mem_controller *ctrl) +{ +} + +// defines S3_NVRAM_EARLY: +#include "southbridge/via/k8t890/k8t890_early_car.c" + +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit_f.c" +#include "lib/generic_sdram.c" + +#include "cpu/amd/dualcore/dualcore.c" + +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" + +#define SB_VFSMAF 0 + +/* this function might fail on some K8 CPUs with errata #181 */ +static void ldtstop_sb(void) +{ + print_debug("toggle LDTSTP#\n"); + u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c); + reg = reg ^ (1 << 0); + outb(reg, VT8237R_ACPI_IO_BASE + 0x5c); + reg = inb(VT8237R_ACPI_IO_BASE + 0x15); + print_debug("done\n"); +} + +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, + (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, + // Node 1 + (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, + (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = + (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8712f_kill_watchdog(); + it8712f_enable_3vsbsw(); + uart_init(); + console_init(); + enable_rom_decode(); + + printk(BIOS_INFO, "now booting... \n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + printk(BIOS_INFO, "now booting... All core 0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + print_debug_hex8(needs_reset); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + print_debug_hex8(needs_reset); + needs_reset |= k8t890_early_setup_ht(); + print_debug_hex8(needs_reset); + + if (needs_reset) { + printk(BIOS_DEBUG, "ht reset -\n"); + soft_reset(); + printk(BIOS_DEBUG, "FAILED!\n"); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* allow LDT STOP asserts */ + vt8237_sb_enable_fid_vid(); + + enable_fid_change(); + print_debug("after enable_fid_change\n"); + + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} + diff -Naru src/mainboard/asus/m2v.none/romstage_m2v-mx_se.c src/mainboard/asus/m2v/romstage_m2v-mx_se.c --- src/mainboard/asus/m2v.none/romstage_m2v-mx_se.c 1970-01-01 01:00:00.000000000 +0100 +++ src/mainboard/asus/m2v/romstage_m2v-mx_se.c 2010-10-20 20:43:15.000000000 +0200 @@ -0,0 +1,213 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) + * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +/* Used by raminit. */ +#define QRANK_DIMM_SUPPORT 1 + +/* Used by init_cpus and fidvid */ +#define SET_FIDVID 1 + +/* If we want to wait for core1 done before DQS training, set it to 0. */ +#define SET_FIDVID_CORE0_ONLY 1 + +#if CONFIG_K8_REV_F_SUPPORT == 1 +#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 +#endif + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/ite/it8712f/it8712f_early_serial.c" +#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +static void activate_spd_rom(const struct mem_controller *ctrl) +{ +} + +// defines S3_NVRAM_EARLY: +#include "southbridge/via/k8t890/k8t890_early_car.c" + +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit_f.c" +#include "lib/generic_sdram.c" + +#include "cpu/amd/dualcore/dualcore.c" + +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" + +#define SB_VFSMAF 0 + +/* this function might fail on some K8 CPUs with errata #181 */ +static void ldtstop_sb(void) +{ + print_debug("toggle LDTSTP#\n"); + u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c); + reg = reg ^ (1 << 0); + outb(reg, VT8237R_ACPI_IO_BASE + 0x5c); + reg = inb(VT8237R_ACPI_IO_BASE + 0x15); + print_debug("done\n"); +} + +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, + (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, + // Node 1 + (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, + (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = + (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8712f_kill_watchdog(); + it8712f_enable_3vsbsw(); + uart_init(); + console_init(); + enable_rom_decode(); + + printk(BIOS_INFO, "now booting... \n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + printk(BIOS_INFO, "now booting... All core 0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + print_debug_hex8(needs_reset); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + print_debug_hex8(needs_reset); + needs_reset |= k8t890_early_setup_ht(); + print_debug_hex8(needs_reset); + + vt8237_early_network_init(NULL); + vt8237_early_spi_init(); + + if (needs_reset) { + printk(BIOS_DEBUG, "ht reset -\n"); + soft_reset(); + printk(BIOS_DEBUG, "FAILED!\n"); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* allow LDT STOP asserts */ + vt8237_sb_enable_fid_vid(); + + enable_fid_change(); + print_debug("after enable_fid_change\n"); + + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} +
Hi, did you get somewhere with your M2V? I'm looking into it right now, but I don't have the vt8237a docs. Coreboot starts initializing HW, but it hangs during the bus scan... Looks like it hangs while trying to scan the pcie bridge 00:02.0 coreboot-4.0-r5976M Thu Oct 21 02:30:11 CEST 2010 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 freq_cap1=0x75, freq_cap2=0x75 dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x1 after optimize_link_read_pointers_chain, reset_needed=0x1 01K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075 01ht reset - soft reset coreboot-4.0-r5976M Thu Oct 21 02:30:11 CEST 2010 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 freq_cap1=0x75, freq_cap2=0x75 dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075 00after enable_fid_change toggle LDTSTP# done Current fid_cur: 0x2, fid_max: 0xc Requested fid_new: 0xc FidVid table step fidvid: 0xc toggle LDTSTP# done FidVid table step fidvid: 0xc toggle LDTSTP# done FidVid table step fidvid: 0xc toggle LDTSTP# done FidVid table step fidvid: 0xc toggle LDTSTP# done FidVid table step fidvid: 0xc toggle LDTSTP# done FidVid table step fidvid: 0xc toggle LDTSTP# done FidVid table step fidvid: 0xc toggle LDTSTP# done FidVid table step fidvid: 0xc toggle LDTSTP# done toggle LDTSTP# done set vid failed for apicid =00 set fid failed for apicid =00 enable_smbus() Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000ceee8 Enabling dual channel memory Unbuffered 266MHz 266MHz Interleaved RAM end at 0x00800000 kB Ram3 Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 2048MB, type WB Setting variable MTRR 3, base: 2048MB, range: 1024MB, type WB Setting variable MTRR 4, base: 3072MB, range: 512MB, type WB Setting variable MTRR 5, base: 3584MB, range: 256MB, type WB Setting variable MTRR 6, base: 3840MB, range: 128MB, type WB Setting variable MTRR 7, base: 3968MB, range: 64MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=06 done DQS Training:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce950 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 done DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=38 done DQS SAVE NVRAM: c2000 Writing 111322 of size 4 to nvram pos: 0 Writing 17181717 of size 4 to nvram pos: 4 Writing 17181817 of size 4 to nvram pos: 8 Writing 17 of size 1 to nvram pos: 12 Writing 342f00 of size 4 to nvram pos: 13 Writing 16161717 of size 4 to nvram pos: 17 Writing 17161717 of size 4 to nvram pos: 21 Writing 17 of size 1 to nvram pos: 25 Writing 35 of size 1 to nvram pos: 26 Writing 38 of size 1 to nvram pos: 27 Writing 0 of size 1 to nvram pos: 28 Writing 0 of size 1 to nvram pos: 29 Writing 111322 of size 4 to nvram pos: 30 Writing 17161617 of size 4 to nvram pos: 34 Writing 17171818 of size 4 to nvram pos: 38 Writing 18 of size 1 to nvram pos: 42 Writing 342f00 of size 4 to nvram pos: 43 Writing 16161615 of size 4 to nvram pos: 47 Writing 18161616 of size 4 to nvram pos: 51 Writing 16 of size 1 to nvram pos: 55 Writing 35 of size 1 to nvram pos: 56 Writing 38 of size 1 to nvram pos: 57 Writing 0 of size 1 to nvram pos: 58 Writing 0 of size 1 to nvram pos: 59 Writing 34108099 of size 4 to nvram pos: 60 DQS Training:tsc[00]=000000006852302d DQS Training:tsc[01]=0000000069705232 DQS Training:tsc[02]=000000006970523b DQS Training:tsc[03]=00000000f0113e95 DQS Training:tsc[04]=00000001021a6006 Ram4 v_esp=000cef28 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading stage image. Check CBFS header at fffffc6e magic is 4f524243 Found CBFS header at fffffc6e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + b461 + align -> fffcb4c0 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (491520 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-r5976M Thu Oct 21 02:30:11 CEST 2010 booting... Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 0 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 0 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 Found Rev E or Rev F later single core CPU: APIC: 00 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: Using configuration type 1 PCI: 00:00.0 [1106/0351] enabled Capability: type 0x01 @ 0x50 Capability: type 0x08 @ 0x60 flags: 0x0060 PCI: 00:00.0 count: 0003 static_count: 0013 PCI: 00:00.0 [1106/0351] enabled next_unitid: 0013 PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1106/0351] enabled malloc Enter, size 68, free_mem_ptr 00138000 malloc 00138000 PCI: 00:00.1 [1106/1351] enabled malloc Enter, size 68, free_mem_ptr 00138044 malloc 00138044 PCI: 00:00.2 [1106/2351] enabled malloc Enter, size 68, free_mem_ptr 00138088 malloc 00138088 PCI: 00:00.3 [1106/3351] enabled malloc Enter, size 68, free_mem_ptr 001380cc malloc 001380cc PCI: 00:00.4 [1106/4351] enabled malloc Enter, size 68, free_mem_ptr 00138110 malloc 00138110 PCI: 00:00.5 [1106/5351] enabled malloc Enter, size 68, free_mem_ptr 00138154 malloc 00138154 PCI: 00:00.6 [1106/6238] enabled malloc Enter, size 68, free_mem_ptr 00138198 malloc 00138198 PCI: 00:00.7 [1106/7351] enabled malloc Enter, size 68, free_mem_ptr 001381dc malloc 001381dc PCI: 00:01.0 [1106/b188] bus ops B188 device dump 00: 06 11 88 b1 07 00 30 02 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 20 02 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 70 00 00 00 00 00 00 00 00 00 16 00 40: 91 40 00 44 31 3a 88 b1 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 0e 70 35 00 07 02 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 08 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: bf 63 08 00 00 00 00 00 00 00 1f c4 00 04 00 00 c0: 08 00 0b ff 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:01.0 [1106/b188] enabled malloc Enter, size 68, free_mem_ptr 00138220 malloc 00138220 PCI: 00:02.0 [1106/a238] bus ops Configuring PCIe PEG 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 18 00 50: 00 00 20 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 b0: 0c 12 c0 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 43 02 27 8a 44 44 44 44 44 44 44 44 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 04 84 50 c2 00 00 00 8f 00 97 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 18 00 50: 00 00 20 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 44 30 f1 7c ff 7f 04 00 00 00 00 00 00 00 00 b0: 0c f0 c0 81 00 00 03 00 01 00 00 00 00 00 00 00 c0: 43 02 27 8a 44 44 44 44 44 44 44 44 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 84 50 c2 00 00 00 8f 00 97 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:02.0 [1106/a238] enabled malloc Enter, size 68, free_mem_ptr 00138264 malloc 00138264 PCI: 00:03.0 [1106/c238] bus ops Configuring PCIe PEXs 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 c1 0e 00 00 00 00 10 00 41 0c 18 01 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 43 4a 27 8a 44 44 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 00 00 22 28 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 c1 0e 00 00 00 00 10 00 41 0c 18 01 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 43 4a 27 8a 44 44 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 00 22 28 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.0 [1106/c238] enabled malloc Enter, size 68, free_mem_ptr 001382a8 malloc 001382a8 PCI: 00:03.1 [1106/d238] bus ops Configuring PCIe PEXs 00: 06 11 38 d2 00 00 10 00 00 00 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 02 00 00 40: 10 68 41 01 81 0f 00 00 00 00 10 00 11 0c 18 02 50: 10 00 00 00 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 18 00 8a 44 44 44 44 00 00 00 00 00 00 00 00 d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0f 00 02 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 00: 06 11 38 d2 00 00 10 00 00 00 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 02 00 00 40: 10 68 41 01 81 0f 00 00 00 00 10 00 11 0c 18 02 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 18 00 8a 44 44 44 44 00 00 00 00 00 00 00 00 d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.1 [1106/d238] enabled malloc Enter, size 68, free_mem_ptr 001382ec malloc 001382ec PCI: 00:03.2 [1106/e238] bus ops Configuring PCIe PEXs 00: 06 11 38 e2 00 00 10 00 00 00 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 03 00 00 40: 10 68 41 01 81 0f 00 00 00 00 10 00 11 0c 18 03 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 00 00 00 8a 04 00 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0c 00 02 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00: 06 11 38 e2 00 00 10 00 00 00 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 03 00 00 40: 10 68 41 01 81 0f 00 00 00 00 10 00 11 0c 18 03 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 00 00 00 8a 04 00 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.2 [1106/e238] enabled malloc Enter, size 68, free_mem_ptr 00138330 malloc 00138330 PCI: 00:03.3 [1106/f238] bus ops Configuring PCIe PEXs 00: 06 11 38 f2 00 00 10 00 00 00 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 04 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 11 0c 18 04 50: 10 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 00 00 00 8a 04 00 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 09 00 02 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00: 06 11 38 f2 00 00 10 00 00 00 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 04 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 11 0c 18 04 50: 00 00 00 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 00 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 44 30 f1 5c ff 7f 04 00 00 00 00 00 00 00 00 b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 00 00 00 8a 04 00 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 00 02 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.3 [1106/f238] enabled malloc Enter, size 68, free_mem_ptr 00138374 malloc 00138374 PCI: 00:0b.0 [102b/0519] enabled malloc Enter, size 68, free_mem_ptr 001383b8 malloc 001383b8 PCI: 00:0f.0 [1106/0591] enabled PCI: 00:0f.1 [1106/0571] ops PCI: 00:0f.1 [1106/0571] enabled malloc Enter, size 68, free_mem_ptr 001383fc malloc 001383fc PCI: 00:10.0 [1106/3038] ops PCI: 00:10.0 [1106/3038] enabled malloc Enter, size 68, free_mem_ptr 00138440 malloc 00138440 PCI: 00:10.1 [1106/3038] ops PCI: 00:10.1 [1106/3038] enabled malloc Enter, size 68, free_mem_ptr 00138484 malloc 00138484 PCI: 00:10.2 [1106/3038] ops PCI: 00:10.2 [1106/3038] enabled malloc Enter, size 68, free_mem_ptr 001384c8 malloc 001384c8 PCI: 00:10.3 [1106/3038] ops PCI: 00:10.3 [1106/3038] enabled malloc Enter, size 68, free_mem_ptr 0013850c malloc 0013850c PCI: 00:10.4 [1106/3104] ops PCI: 00:10.4 [1106/3104] enabled PCI: 00:11.0 [1106/3337] enabled malloc Enter, size 68, free_mem_ptr 00138550 malloc 00138550 PCI: 00:11.7 [1106/287e] ops PCI: 00:11.7 [1106/287e] enabled do_pci_scan_bridge for PCI: 00:01.0 malloc Enter, size 24, free_mem_ptr 00138594 malloc 00138594 PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:02.0 malloc Enter, size 24, free_mem_ptr 001385ac malloc 001385ac PCI: pci_scan_bus for bus 02 [hangs here] Patch so far (mostly copied from a8v-e_se and m2v-mx_se):