From patchwork Fri Oct 22 01:34:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: fix unexpacted MTRR setup for UMA memory Date: Fri, 22 Oct 2010 01:34:29 -0000 From: Scott X-Patchwork-Id: 2158 Message-Id: To: Hello, I find an unexpected MTRR setup for my RS780/SB700 UMA board. With a single 1GB DIMM and 256MB UMA size, the variable MTRRs look like this: -----coreboot+seabios----- default memory type: UC variable range 0: 000000000-03FFFFFFF WB variable range 1: 040000000-04FFFFFFF WB variable range 2: 030000000-03FFFFFFF UC variable range 3: disabled variable range 4: disabled variable range 5: disabled variable range 6: disabled variable range 7: disabled Variable range 1 is unexpected. It creates a window of WB-IO, which is highly unusual. -----Production BIOS (AMI):----- default memory type: UC variable range 0: 000000000-01FFFFFFF WB variable range 1: 020000000-02FFFFFFF WB variable range 2: disabled variable range 3: disabled variable range 4: disabled variable range 5: disabled variable range 6: disabled variable range 7: disabled The above is how uma is normally handled. Build up WB ranges until the needed size is reached. -----[patched] coreboot+seabios----- default memory type: UC variable range 0: 000000000-01FFFFFFF WB variable range 1: 020000000-02FFFFFFF WB variable range 2: disabled variable range 3: disabled variable range 4: disabled variable range 5: disabled variable range 6: disabled variable range 7: disabled With the patch, coreboot matches the production BIOS. Signed-off-by: Scott Duplichan Index: src/cpu/x86/mtrr/mtrr.c =================================================================== --- src/cpu/x86/mtrr/mtrr.c (revision 5978) +++ src/cpu/x86/mtrr/mtrr.c (working copy) @@ -423,11 +423,8 @@ if (var_state.hole_startk || var_state.hole_sizek) { printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n"); } else { - // Increase the base range and set up UMA as an UC hole instead - var_state.range_sizek += (uma_memory_size >> 10); - - var_state.hole_startk = (uma_memory_base >> 10); - var_state.hole_sizek = (uma_memory_size >> 10); + // Reduce the dram wb mtrr range so that it does not cover the uma at the end + var_state.range_sizek -= (uma_memory_size >> 10); } #endif /* Write the last range */ Index: src/cpu/x86/mtrr/mtrr.c =================================================================== --- src/cpu/x86/mtrr/mtrr.c (revision 5978) +++ src/cpu/x86/mtrr/mtrr.c (working copy) @@ -423,11 +423,8 @@ if (var_state.hole_startk || var_state.hole_sizek) { printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n"); } else { - // Increase the base range and set up UMA as an UC hole instead - var_state.range_sizek += (uma_memory_size >> 10); - - var_state.hole_startk = (uma_memory_base >> 10); - var_state.hole_sizek = (uma_memory_size >> 10); + // Reduce the dram wb mtrr range so that it does not cover the uma at the end + var_state.range_sizek -= (uma_memory_size >> 10); } #endif /* Write the last range */