Submitter | Scott |
---|---|
Date | 2010-10-22 21:01:26 |
Message ID | <0C5CDCBCD5F74440BB7BE8B8AC46DFB3@m3a78> |
Download | mbox | patch |
Permalink | /patch/2161/ |
State | Superseded |
Headers | show |
Comments
On 22.10.2010, at 14:01, "Scott Duplichan" <scott@notabs.org> wrote: > A patch that gets rid of the unexpected variable MTRR range while > still using the carve out method of making UMA DRAM UC is easy enough > (see below). > > What are the chances that this patch fixes the AMD family 10h systems > but breaks others? Is there someone here with a non-AMD UMA system? > If so, it would be useful if you could load it with _less_ than 4GB > of memory and then dump the variable MTRRs. If it also has the > unexpected MTRR range, then patching mtrr.c is probably the right > thing to do. > > Thanks, > Scott > > Signed-off-by: Scott Duplichan <scott@notabs.org> > > Index: src/cpu/x86/mtrr/mtrr.c > =================================================================== > --- src/cpu/x86/mtrr/mtrr.c (revision 5978) > +++ src/cpu/x86/mtrr/mtrr.c (working copy) > @@ -423,9 +423,7 @@ > if (var_state.hole_startk || var_state.hole_sizek) { > printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n"); > } else { > - // Increase the base range and set up UMA as an UC hole instead > - var_state.range_sizek += (uma_memory_size >> 10); > - > + // Set up UMA as an UC hole > var_state.hole_startk = (uma_memory_base >> 10); > var_state.hole_sizek = (uma_memory_size >> 10); > } I think the problem you are seeing might be that on some chipsets the memory resource still contains the UMA part of that memory while on others it just contains the usable memory. That would explain why removing that particular line from the code would solve the problem for you. Not sure what the right solution would be but we should make sure that it's consistent across chipsets.. Stefan
Hi, I just want to tell "me too", so question is we go to direction of claiming less ram_resource as intel do or others. Is the AMD uma limited to < 4GB? Thanks, Rudolf
-----Original Message-----
From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Rudolf Marek
Sent: Wednesday, November 03, 2010 06:07 PM
To: coreboot@coreboot.org
Subject: Re: [coreboot] [patch] fix unexpacted MTRR setup for UMA memory
]Hi,
]
]I just want to tell "me too", so question is we go to direction of claiming less
]ram_resource as intel do or others.
So far there has been no comments about non-AMD UMA systems. This is one of several
items that need to be resolved before the trunk can support Win7 for AMS UMA systems.
]Is the AMD uma limited to < 4GB?
The RS780 frame buffer can be placed above 4GB. I remember booting a
Tilapia board a while back and finding the frame buffer is above 4GB
by default. A setup option can be used to select above or below.
]Thanks,
]Rudolf
Patch
Index: src/cpu/x86/mtrr/mtrr.c =================================================================== --- src/cpu/x86/mtrr/mtrr.c (revision 5978) +++ src/cpu/x86/mtrr/mtrr.c (working copy) @@ -423,9 +423,7 @@ if (var_state.hole_startk || var_state.hole_sizek) { printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n"); } else { - // Increase the base range and set up UMA as an UC hole instead - var_state.range_sizek += (uma_memory_size >> 10); - + // Set up UMA as an UC hole var_state.hole_startk = (uma_memory_base >> 10); var_state.hole_sizek = (uma_memory_size >> 10); }