Add support for K8T890CF, VT8237A and ASUS M2V board.
Needs crosschecking on VT8237R and VT8237S,
since I had to touch some common codepaths like in
src/southbridge/via/vt8237r/vt8237r_early_smbus.c
Also because of the changed PCIe init code.
Stupid issues that caused way too much (~1 day) headscratching until fixed:
- I forgot to add the pci id in vt8237r_lpc.c:
It was booting, but interrupts didn't work
- I didn't have the 13.0 and 13.1 bridges in devicetree.cb:
Linux saw the 13.0 bridge, but not the coreboot device scan.
When enabling the 13.1 bridge, VGA init failed, since coreboot didn't see
and initialize the bridge.
Tested:
- Linux boot (ACPI, APIC and LAPIC enabled) with acpi/mptables-enabled coreboot
- HPET (detected and seems to work)
- Serial port works
- PCI slot irq routing works
- PCIe slot irq routing works
- MMCONFIG for extended pcie config space works
- Booting from IDE HDD/CDROM works
- Seabios won't boot from SATA, but both SATA controllers work in Linux
- All 8 USB ports work
FIXME:
- PCIe doesn't get initialized on cold boot, only works when warm rebooting
into Coreboot from Machine booted by AMI BIOS
Someone with Datasheets needs to have a look I think
- Onboard sound spews lots of "hda-intel: spurious response" messages and
times out eventually. So for now we disable the bridge
- VLINK settings works for me, but I don't have Datasheets
Signed-Off-By: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
===================================================================
@@ -37,6 +37,9 @@
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
if (!devfun3)
+ devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
+ if (!devfun3)
die("Unknown NB");
/* CPU to PCI Flow Control 1 & 2, just fill in recommended. */
@@ -109,6 +112,9 @@
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
+ if (!devfun7)
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
/* No pairing NB was found. */
if (!devfun7)
return;
@@ -162,6 +168,69 @@
}
+static void vt8237a_vlink_init(struct device *dev)
+{
+ u8 reg;
+ device_t devfun7;
+
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+ if (!devfun7)
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
+ if (!devfun7)
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
+ /* No pairing NB was found. */
+ if (!devfun7)
+ return;
+
+ /*
+ * This init code is valid only for the VT8237A! For different
+ * sounthbridges (e.g. VT8237S, VT8237R (without plus R)
+ * and VT8251) a different init code is required.
+ */
+
+ /* disable auto disconnect */
+ reg = pci_read_config8(devfun7, 0x42);
+ reg &= ~0x4;
+ pci_write_config8(devfun7, 0x42, reg);
+
+ /* NB part setup */
+ pci_write_config8(devfun7, 0xb5, 0x88);
+ pci_write_config8(devfun7, 0xb6, 0x88);
+ pci_write_config8(devfun7, 0xb7, 0x61);
+
+ reg = pci_read_config8(devfun7, 0xb4);
+ reg |= 0x11;
+ pci_write_config8(devfun7, 0xb4, reg);
+
+ pci_write_config8(devfun7, 0xb0, 0x6);
+ pci_write_config8(devfun7, 0xb1, 0x1);
+
+ /* SB part setup */
+ pci_write_config8(dev, 0xb7, 0x50);
+ pci_write_config8(dev, 0xb9, 0x88);
+ pci_write_config8(dev, 0xba, 0x8a);
+ pci_write_config8(dev, 0xbb, 0x88);
+
+ reg = pci_read_config8(dev, 0xbd);
+ reg |= 0x3;
+ reg &= ~0x4;
+ pci_write_config8(dev, 0xbd, reg);
+
+ reg = pci_read_config8(dev, 0xbc);
+ reg &= ~0x7;
+ pci_write_config8(dev, 0xbc, reg);
+
+ pci_write_config8(dev, 0x48, 0x23);
+
+ /* enable auto disconnect, for STPGNT and HALT */
+ reg = pci_read_config8(devfun7, 0x42);
+ reg |= 0x7;
+ pci_write_config8(devfun7, 0x42, reg);
+}
+
static void ctrl_enable(struct device *dev)
{
/* Enable the 0:13 and 0:13.1. */
@@ -187,6 +256,12 @@
vt8237s_vlink_init(dev);
}
+ devsb = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);
+ if (devsb) {
+ vt8237a_vlink_init(dev);
+ }
+
/* Configure PCI1 and copy mirror registers from D0F3. */
vt8237_cfg(dev);
dump_south(dev);
===================================================================
@@ -134,6 +134,29 @@
#define PSONREADY_TIMEOUT 0x7fffffff
+static device_t get_vt8237_lpc(void)
+{
+ device_t dev;
+
+ /* Power management controller */
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+ if (dev != PCI_DEV_INVALID)
+ return dev;
+
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
+ if (dev != PCI_DEV_INVALID)
+ return dev;
+
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);
+ if (dev == PCI_DEV_INVALID)
+ die("VT8237 Power management controller not found\n");
+
+ return dev;
+}
+
/**
* Enable the SMBus on VT8237R-based systems.
*/
@@ -143,15 +166,7 @@
int loops;
/* Power management controller */
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
- if (dev == PCI_DEV_INVALID) {
- /* Power management controller */
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
- if (dev == PCI_DEV_INVALID)
- die("Power management controller not found\n");
- }
+ dev = get_vt8237_lpc();
/* Make sure the RTC power well is up before touching smbus. */
loops = 0;
@@ -236,44 +251,17 @@
{
device_t dev, devctl;
- /* Power management controller */
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
- if (dev == PCI_DEV_INVALID) {
- /* Power management controller */
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
- if (dev == PCI_DEV_INVALID)
- return;
+ devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
- devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
-
- if (devctl == PCI_DEV_INVALID)
- return;
-
- /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
- pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
-
- /* Enable ACPI accessm RTC signal gated with PSON. */
- pci_write_config8(dev, 0x81, 0x84);
-
- /*
- * Allow SLP# signal to assert LDTSTOP_L.
- * Will work for C3 and for FID/VID change.
- */
-
- outb(0xff, VT8237R_ACPI_IO_BASE + 0x50);
-
- /* Reduce further the STPCLK/LDTSTP signal to 5us. */
- pci_write_config8(dev, 0xec, 0x4);
-
+ if (devctl) {
/* So the chip knows we are on AMD. */
pci_write_config8(devctl, 0x7c, 0x7f);
-
- return;
}
+ /* Power management controller */
+ dev = get_vt8237_lpc();
+
/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
@@ -285,6 +273,16 @@
* Will work for C3 and for FID/VID change.
*/
outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
+
+ if (pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237S_LPC), 0) !=
+ PCI_DEV_INVALID) {
+ /* VT8237S */
+ outb(0xff, VT8237R_ACPI_IO_BASE + 0x50);
+ } else {
+ /* VT8237R or VT8237A */
+ outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
+ }
}
void enable_rom_decode(void)
@@ -292,15 +290,7 @@
device_t dev;
/* Power management controller */
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
- if (dev == PCI_DEV_INVALID) {
- /* Power management controller */
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
- if (dev == PCI_DEV_INVALID)
- return;
- }
+ dev = get_vt8237_lpc();
/* ROM decode last 1MB FFC00000 - FFFFFFFF. */
pci_write_config8(dev, 0x41, 0x7f);
@@ -315,16 +305,7 @@
print_debug("IN TEST WAKEUP\n");
- /* Power management controller */
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
- if (dev == PCI_DEV_INVALID) {
- /* Power management controller */
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
- if (dev == PCI_DEV_INVALID)
- die("Power management controller not found\n");
- }
+ dev = get_vt8237_lpc();
/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
===================================================================
@@ -319,6 +319,60 @@
printk(BIOS_SPEW, "Leaving %s.\n", __func__);
}
+static void vt8237a_init(struct device *dev)
+{
+ u32 tmp;
+ device_t pdev;
+
+ /* Set bit 3 of 0x4f (use INIT# as CPU reset). */
+ tmp = pci_read_config8(dev, 0x4f);
+ tmp |= 0x08;
+ pci_write_config8(dev, 0x4f, tmp);
+
+ /*
+ * bit2: REQ5 as PCI request input - should be together with INTE-INTH.
+ * bit5: usb power control lines as gpio
+ */
+ pci_write_config8(dev, 0xe4, 0x24);
+ /*
+ * Enable APIC wakeup from INTH
+ * Enable SATA LED, disable special CPU Frequency Change -
+ * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
+ */
+ pci_write_config8(dev, 0xe5, 0x69);
+
+ /* Reduce further the STPCLK/LDTSTP signal to 5us. */
+ pci_write_config8(dev, 0xec, 0x4);
+
+ /* Host Bus Power Management Control, maybe not needed */
+ pci_write_config8(dev, 0x8c, 0x5);
+
+ /* Enable HPET at VT8237R_HPET_ADDR. */
+ pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80));
+
+ southbridge_init_common(dev);
+
+ /* FIXME: Intel needs more bit set for C2/C3. */
+
+ /*
+ * Allow SLP# signal to assert LDTSTOP_L.
+ * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2.
+ */
+ outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
+
+ /* FIXME: Azalia not working yet, disable audio device */
+ pdev = dev_find_device(PCI_VENDOR_ID_VIA,
+ 0x337b, 0);
+ if (pdev) {
+ printk(BIOS_DEBUG, "FIXME: Azalia audio not working yet, disabled.\n");
+ tmp = pci_read_config8(pdev, 0x42);
+ tmp |= 8;
+ pci_write_config8(pdev, 0x42, tmp);
+ }
+
+ dump_south(dev);
+}
+
static void vt8237s_init(struct device *dev)
{
u32 tmp;
@@ -408,7 +462,7 @@
/* I/O recovery time, default IDE routing */
pci_write_config8(dev, 0x4c, 0x04);
- /* ROM memory cycles go to LPC. */
+ /* Only ROM memory cycles go to LPC. */
pci_write_config8(dev, 0x59, 0x80);
/*
@@ -430,7 +484,7 @@
/* I/O recovery time, default IDE routing */
pci_write_config8(dev, 0x4c, 0x44);
- /* ROM memory cycles go to LPC. */
+ /* Only ROM memory cycles go to LPC. */
pci_write_config8(dev, 0x59, 0x80);
/*
@@ -537,12 +591,26 @@
.scan_bus = scan_static_bus,
};
+static const struct device_operations vt8237r_lpc_ops_a = {
+ .read_resources = vt8237r_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = vt8237a_init,
+ .scan_bus = scan_static_bus,
+};
+
static const struct pci_driver lpc_driver_r __pci_driver = {
.ops = &vt8237r_lpc_ops_r,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_VT8237R_LPC,
};
+static const struct pci_driver lpc_driver_a __pci_driver = {
+ .ops = &vt8237r_lpc_ops_a,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VT8237A_LPC,
+};
+
static const struct pci_driver lpc_driver_s __pci_driver = {
.ops = &vt8237r_lpc_ops_s,
.vendor = PCI_VENDOR_ID_VIA,
===================================================================
@@ -76,6 +76,12 @@
.device = PCI_DEVICE_ID_VIA_K8T890CE_0,
};
+static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+ .ops = &host_ops_t,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T890CF_0,
+};
+
static const struct pci_driver northbridge_driver_m __pci_driver = {
.ops = &host_ops_m,
.vendor = PCI_VENDOR_ID_VIA,
===================================================================
@@ -144,6 +144,12 @@
.device = PCI_DEVICE_ID_VIA_K8T890CE_5,
};
+static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+ .ops = &traf_ctrl_ops_t,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T890CF_5,
+};
+
static const struct pci_driver northbridge_driver_m __pci_driver = {
.ops = &traf_ctrl_ops_m,
.vendor = PCI_VENDOR_ID_VIA,
===================================================================
@@ -35,6 +35,10 @@
reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg | 0x10);
+ /* needed for asus m2v / k8t890cf or bus scan will hang */
+ reg = pci_read_config8(dev, 0xa3);
+ pci_write_config8(dev, 0xa3, reg & ~0x01);
+
/* Award has 0xb, VIA recomends 0x4. */
pci_write_config8(dev, 0xe1, 0xb);
@@ -75,6 +79,10 @@
reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg | 0x10);
+ /* needed for asus m2v / k8t890cf or bus scan will hang */
+ reg = pci_read_config8(dev, 0xa3);
+ pci_write_config8(dev, 0xa3, reg & ~0x01);
+
/* Award has 0xb, VIA recommends 0x4. */
pci_write_config8(dev, 0xe1, 0xb);
/* Set replay timer limit. */
===================================================================
@@ -170,6 +170,12 @@
.device = PCI_DEVICE_ID_VIA_K8T890CE_3,
};
+static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+ .ops = &dram_ops_t,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T890CF_3,
+};
+
static const struct pci_driver northbridge_driver_m __pci_driver = {
.ops = &dram_ops_m,
.vendor = PCI_VENDOR_ID_VIA,
===================================================================
@@ -48,6 +48,12 @@
.device = PCI_DEVICE_ID_VIA_K8T890CE_1,
};
+static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+ .ops = &error_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T890CF_1,
+};
+
static const struct pci_driver northbridge_driver_m __pci_driver = {
.ops = &error_ops,
.vendor = PCI_VENDOR_ID_VIA,
===================================================================
@@ -36,10 +36,17 @@
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
- if (!devfun3)
- devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+ if (!devfun3)
+ devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
+
+ if (!devfun3)
+ devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
+ if (!devfun3)
+ die("vt8237r_cfg: devfun3 not found!");
+
pci_write_config8(dev, 0x70, 0xc2);
/* PCI Control */
@@ -150,7 +157,11 @@
pci_write_config8(dev, 0x47, 0x30);
- /* VT8237R specific configuration other SB are done in their own directories */
+ /*
+ * VT8237R specific configuration,
+ * other SB are done in their own directories:
+ * VT8237A and VT8237S are handled in vt8237_ctrl.c
+ */
device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
@@ -175,6 +186,12 @@
.device = PCI_DEVICE_ID_VIA_K8T890CE_7,
};
+static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+ .ops = &ctrl_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T890CF_7,
+};
+
static const struct pci_driver northbridge_driver_m __pci_driver = {
.ops = &ctrl_ops,
.vendor = PCI_VENDOR_ID_VIA,
===================================================================
@@ -1204,6 +1204,13 @@
#define PCI_DEVICE_ID_VIA_K8T890CE_4 0x4238
#define PCI_DEVICE_ID_VIA_K8T890CE_5 0x5238
#define PCI_DEVICE_ID_VIA_K8T890CE_7 0x7238
+#define PCI_DEVICE_ID_VIA_K8T890CF_0 0x0351
+#define PCI_DEVICE_ID_VIA_K8T890CF_1 0x1351
+#define PCI_DEVICE_ID_VIA_K8T890CF_2 0x2351
+#define PCI_DEVICE_ID_VIA_K8T890CF_3 0x3351
+#define PCI_DEVICE_ID_VIA_K8T890CF_4 0x4351
+#define PCI_DEVICE_ID_VIA_K8T890CF_5 0x5351
+#define PCI_DEVICE_ID_VIA_K8T890CF_7 0x7351
#define PCI_DEVICE_ID_VIA_K8M890CE_0 0x0336
#define PCI_DEVICE_ID_VIA_K8M890CE_1 0x1336
#define PCI_DEVICE_ID_VIA_K8M890CE_2 0x2336
@@ -1219,6 +1226,7 @@
#define PCI_DEVICE_ID_VIA_K8T890CE_BR 0xb188
#define PCI_DEVICE_ID_VIA_VT6420_SATA 0x3149
#define PCI_DEVICE_ID_VIA_VT8237R_LPC 0x3227
+#define PCI_DEVICE_ID_VIA_VT8237A_LPC 0x3337
#define PCI_DEVICE_ID_VIA_VT8237S_LPC 0x3372
#define PCI_DEVICE_ID_VIA_VT8237_SATA 0x5372
#define PCI_DEVICE_ID_VIA_VT8237_VLINK 0x287e
===================================================================
@@ -25,6 +25,8 @@
bool "A8N-E"
config BOARD_ASUS_A8V_E_SE
bool "A8V-E SE"
+config BOARD_ASUS_M2V
+ bool "M2V"
config BOARD_ASUS_M2V_MX_SE
bool "M2V-MX SE"
config BOARD_ASUS_M4A785M
@@ -50,6 +52,7 @@
source "src/mainboard/asus/a8n_e/Kconfig"
source "src/mainboard/asus/a8v-e_se/Kconfig"
+source "src/mainboard/asus/m2v/Kconfig"
source "src/mainboard/asus/m2v-mx_se/Kconfig"
source "src/mainboard/asus/m4a785-m/Kconfig"
source "src/mainboard/asus/mew-am/Kconfig"
===================================================================
@@ -0,0 +1,78 @@
+if BOARD_ASUS_M2V
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_AMD_SOCKET_AM2
+ select DIMM_DDR2
+ select K8_HT_FREQ_1G_SUPPORT
+ select NORTHBRIDGE_AMD_AMDK8
+ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+ select SOUTHBRIDGE_VIA_VT8237R
+ select SOUTHBRIDGE_VIA_K8T890
+ select SUPERIO_ITE_IT8712F
+ select CACHE_AS_RAM
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_TABLES
+ select HAVE_MP_TABLE
+ select BOARD_ROMSIZE_KB_512
+ select RAMINIT_SYSINFO
+ select TINY_BOOTBLOCK
+
+config MAINBOARD_DIR
+ string
+ default asus/m2v
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xcc000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x4000
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+ hex
+ default 0x1000
+
+config APIC_ID_OFFSET
+ hex
+ default 0x10
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 1
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "M2V"
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0
+
+config MAX_CPUS
+ int
+ default 2
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 1
+
+config HEAP_SIZE
+ hex
+ default 0x40000
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x20
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0x0
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1043
+
+endif # BOARD_ASUS_M2V
===================================================================
@@ -0,0 +1,74 @@
+chip northbridge/amd/amdk8/root_complex # Root complex
+ device lapic_cluster 0 on # APIC cluster
+ chip cpu/amd/socket_AM2 # CPU
+ device lapic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ chip northbridge/amd/amdk8 # mc0
+ device pci 18.0 on # Northbridge
+ # Devices on link 0, link 0 == LDT 0
+ chip southbridge/via/vt8237r # Southbridge
+ register "ide0_enable" = "1" # Enable IDE channel 0
+ register "ide1_enable" = "1" # Enable IDE channel 1
+ register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
+ register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
+ register "fn_ctrl_lo" = "0xc0" # Enable SB functions
+ register "fn_ctrl_hi" = "0x0d" # Enable SB functions
+ device pci 0.0 on end # HT
+ device pci f.1 on end # IDE
+ device pci 11.0 on # LPC
+ chip drivers/generic/generic # DIMM 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic # DIMM 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic # DIMM 0-1-1
+ device i2c 53 on end
+ end
+ chip superio/ite/it8712f # Super I/O
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off end # Com2 (N/A on this board)
+ device pnp 2e.3 on # Lpt1
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.4 on # Environment controller
+ io 0x60 = 0xd00
+ io 0x62 = 0xc00
+ irq 0x70 = 0x00
+ end
+ device pnp 2e.5 off end # PS/2 keyboard
+ device pnp 2e.6 off end # PS/2 mouse
+ device pnp 2e.7 off end # GPIO config
+ device pnp 2e.8 off end # Midi port
+ device pnp 2e.9 off end # Game port
+ device pnp 2e.a off end # IR
+ end
+ end
+ device pci 12.0 off end # VIA LAN (off, other chip used)
+ device pci 13.0 on end # br
+ device pci 13.1 on end # br2, need to have it here to discover it
+ end
+ chip southbridge/via/k8t890 # "Southbridge" K8T890
+ end
+ end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
===================================================================
@@ -0,0 +1,210 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 AMD
+ * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
+ * Copyright (C) 2006 MSI
+ * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
+ * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+unsigned int get_sbdn(unsigned bus);
+
+/* Used by raminit. */
+#define QRANK_DIMM_SUPPORT 1
+
+/* Used by init_cpus and fidvid */
+#define SET_FIDVID 1
+
+/* If we want to wait for core1 done before DQS training, set it to 0. */
+#define SET_FIDVID_CORE0_ONLY 1
+
+#if CONFIG_K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/ite/it8712f/it8712f_early_serial.c"
+#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+static void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+// defines S3_NVRAM_EARLY:
+#include "southbridge/via/k8t890/k8t890_early_car.c"
+
+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/raminit_f.c"
+#include "lib/generic_sdram.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#define SB_VFSMAF 0
+
+/* this function might fail on some K8 CPUs with errata #181 */
+static void ldtstop_sb(void)
+{
+ print_debug("toggle LDTSTP#\n");
+ u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
+ reg = reg ^ (1 << 0);
+ outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
+ reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
+ print_debug("done\n");
+}
+
+#include "cpu/amd/model_fxx/fidvid.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
+
+void soft_reset(void)
+{
+ uint8_t tmp;
+
+ set_bios_reset();
+ print_debug("soft reset \n");
+
+ /* PCI reset */
+ tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
+ tmp |= 0x01;
+ /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
+ pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
+
+ while (1) {
+ /* daisy daisy ... */
+ hlt();
+ }
+}
+
+unsigned int get_sbdn(unsigned bus)
+{
+ device_t dev;
+
+ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
+ return (dev >> 15) & 0x1f;
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ static const uint16_t spd_addr[] = {
+ // Node 0
+ (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
+ (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+ // Node 1
+ (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
+ (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+ };
+ unsigned bsp_apicid = 0;
+ int needs_reset = 0;
+ struct sys_info *sysinfo =
+ (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+ it8712f_24mhz_clkin();
+ it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ it8712f_kill_watchdog();
+ uart_init();
+ console_init();
+ enable_rom_decode();
+
+ printk(BIOS_INFO, "now booting... \n");
+
+ if (bist == 0)
+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+
+ /* Halt if there was a built in self test failure. */
+ report_bist_failure(bist);
+ setup_default_resource_map();
+ setup_coherent_ht_domain();
+ wait_all_core0_started();
+
+ printk(BIOS_INFO, "now booting... All core 0 started\n");
+
+#if CONFIG_LOGICAL_CPUS==1
+ /* It is said that we should start core1 after all core0 launched. */
+ start_other_cores();
+ wait_all_other_cores_started(bsp_apicid);
+#endif
+ init_timer();
+ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
+
+ needs_reset = optimize_link_coherent_ht();
+ print_debug_hex8(needs_reset);
+ needs_reset |= optimize_link_incoherent_ht(sysinfo);
+ print_debug_hex8(needs_reset);
+ needs_reset |= k8t890_early_setup_ht();
+ print_debug_hex8(needs_reset);
+
+ if (needs_reset) {
+ printk(BIOS_DEBUG, "ht reset -\n");
+ soft_reset();
+ printk(BIOS_DEBUG, "FAILED!\n");
+ }
+
+ /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
+ /* allow LDT STOP asserts */
+ vt8237_sb_enable_fid_vid();
+
+ enable_fid_change();
+ print_debug("after enable_fid_change\n");
+
+ init_fidvid_bsp(bsp_apicid);
+
+ /* Stop the APs so we can start them later in init. */
+ allow_all_aps_stop(bsp_apicid);
+
+ /* It's the time to set ctrl now. */
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+ enable_smbus();
+ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+ post_cache_as_ram();
+}
+
===================================================================
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include "southbridge/via/vt8237r/vt8237r.h"
+#include "southbridge/via/k8t890/k8t890.h"
+
+static void *smp_write_config_table(void *v)
+{
+ static const char sig[4] = "PCMP";
+ static const char oem[8] = "COREBOOT";
+ static const char productid[12] = "M2V ";
+ struct mp_config_table *mc;
+ int bus_isa = 42;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ memset(mc, 0, sizeof(*mc));
+
+ memcpy(mc->mpc_signature, sig, sizeof(sig));
+ mc->mpc_length = sizeof(*mc); /* Initially just the header. */
+ mc->mpc_spec = 0x04;
+ mc->mpc_checksum = 0; /* Not yet computed. */
+ memcpy(mc->mpc_oem, oem, sizeof(oem));
+ memcpy(mc->mpc_productid, productid, sizeof(productid));
+ mc->mpc_oemptr = 0;
+ mc->mpc_oemsize = 0;
+ mc->mpc_entry_count = 0; /* No entries yet. */
+ mc->mpc_lapic = LAPIC_ADDR;
+ mc->mpe_length = 0;
+ mc->mpe_checksum = 0;
+ mc->reserved = 0;
+
+ smp_write_processors(mc);
+
+
+ /* Bus: Bus ID Type */
+ smp_write_bus(mc, 0, "PCI "); /* root bus */
+ smp_write_bus(mc, 1, "PCI "); /* ??? */
+ smp_write_bus(mc, 2, "PCI "); /* pcie x16 */
+ smp_write_bus(mc, 3, "PCI "); /* pcie x1 */
+ smp_write_bus(mc, 4, "PCI "); /* pcie x1 */
+ smp_write_bus(mc, 5, "PCI "); /* pcie x1 */
+ smp_write_bus(mc, 6, "PCI "); /* pcie x1 */
+ smp_write_bus(mc, 7, "PCI "); /* azalia audio */
+ smp_write_bus(mc, 8, "PCI "); /* pci */
+ smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
+
+ mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
+
+ /* peg bridge */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
+
+ /* pex bridge */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
+
+ /* SATA / IDE */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x15);
+
+ /* USB */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x14);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x16);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 3, VT8237R_APIC_ID, 0x17);
+
+ /* PCIE graphics */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
+
+ /* onboard PCIE atl1 ethernet */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
+
+ /* PCIE slot */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
+
+ /* onboard marvell sata */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
+
+ /* n/a */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
+
+ /* azalia audio */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x7, (0x01 << 2) | 0, VT8237R_APIC_ID, 0x11);
+
+ /* pci slot 1 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x6 << 2) | 0, VT8237R_APIC_ID, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x6 << 2) | 1, VT8237R_APIC_ID, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x6 << 2) | 2, VT8237R_APIC_ID, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x6 << 2) | 3, VT8237R_APIC_ID, 0x13);
+
+ /* pci slot 2 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x7 << 2) | 0, VT8237R_APIC_ID, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x7 << 2) | 1, VT8237R_APIC_ID, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x7 << 2) | 2, VT8237R_APIC_ID, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x7 << 2) | 3, VT8237R_APIC_ID, 0x10);
+
+ /* pci slot 3 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x8 << 2) | 0, VT8237R_APIC_ID, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x8 << 2) | 1, VT8237R_APIC_ID, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x8 << 2) | 2, VT8237R_APIC_ID, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x8 << 2) | 3, VT8237R_APIC_ID, 0x11);
+
+ /* pci slot 4 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x8 << 2) | 0, VT8237R_APIC_ID, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x8 << 2) | 1, VT8237R_APIC_ID, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x8 << 2) | 2, VT8237R_APIC_ID, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x8, (0x8 << 2) | 3, VT8237R_APIC_ID, 0x12);
+
+ /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums. */
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
+ mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
===================================================================
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Written by Stefan Reinauer <stepan@openbios.org>.
+ * ACPI FADT, FACS, and DSDT table support added by
+ *
+ * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
+ * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include "southbridge/via/vt8237r/vt8237r.h"
+#include "southbridge/via/k8t890/k8t890.h"
+
+extern const unsigned char AmlCode[];
+
+static void acpi_create_via_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR 0xfed00000ULL
+ acpi_header_t *header = &(hpet->header);
+ acpi_addr_t *addr = &(hpet->addr);
+
+ memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+ /* fill out header fields */
+ memcpy(header->signature, "HPET", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_hpet_t);
+ header->revision = 1;
+
+ /* fill out HPET address */
+ // XXX factory bios just puts an address here -- who's right?
+ addr->space_id = 0; /* Memory */
+ addr->bit_width = 64;
+ addr->bit_offset = 0;
+ addr->addrl = HPET_ADDR & 0xffffffff;
+ addr->addrh = HPET_ADDR >> 32;
+
+ hpet->id = 0x11068201; /* VIA */
+ hpet->number = 0x00;
+ hpet->min_tick = 0x0090;
+
+ header->checksum =
+ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ device_t dev;
+ struct resource *res;
+
+ dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_5, 0);
+ if (!dev)
+ return current;
+
+ res = find_resource(dev, K8T890_MMCONFIG_MBAR);
+ if (res) {
+ current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
+ current, res->base, 0x0, 0x0, 0xff);
+ }
+ return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ unsigned int gsi_base = 0x18;
+
+ /* Create all subtables for processors. */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write SB IOAPIC. */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ VT8237R_APIC_ID, IO_APIC_ADDR, 0);
+
+ /* Write NB IOAPIC. */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
+
+ /* IRQ9 ACPI active low. */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+
+ /* IRQ0 -> APIC IRQ2. */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0x0);
+
+ /* Create all subtables for processors. */
+ current = acpi_create_madt_lapic_nmis(current,
+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
+
+ return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_srat_t *srat;
+ acpi_rsdt_t *rsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+
+ /* Align ACPI tables to 16 byte. */
+ start = (start + 0x0f) & -0x10;
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT table. */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* Clear all table memory. */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /* We explicitly add these tables later on: */
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ dsdt = (acpi_header_t *)current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ dsdt->checksum = 0; /* Don't trust iasl to get this right. */
+ dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ acpi_create_via_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+ /* If we want to use HPET timers Linux wants it in MADT. */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ acpi_add_table(rsdp, mcfg);
+
+ printk(BIOS_DEBUG, "ACPI: * SRAT\n");
+ srat = (acpi_srat_t *) current;
+ acpi_create_srat(srat);
+ current += srat->header.length;
+ acpi_add_table(rsdp, srat);
+
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
===================================================================
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
===================================================================
@@ -0,0 +1,294 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE", "COREBOOT", 1)
+{
+ /* Define the main processor.*/
+ Scope (\_PR)
+ {
+ Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
+ Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
+ }
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * Any others would involve declaring the wake up methods.
+ */
+ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+ Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
+
+ /* Root of the bus hierarchy */
+ Scope (\_SB)
+ {
+ /* Top PCI device */
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x00)
+
+ /* PCI Routing Table */
+ /* aaa */
+ Name (_PRT, Package () {
+ /* PCI Slots if 13.1 is disabled */
+ /*
+ Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 },
+ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
+ Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 },
+ Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
+ Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
+ Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 },
+ Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
+ Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
+ Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
+ */
+ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 }, /* 0xf SATA IRQ 21 */
+ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x15 }, /* 0xf Native IDE IRQ 21 */
+ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x14 }, /* USB routing */
+ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x16 },
+ Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
+ Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x17 },
+
+ Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 },
+ Package (0x04) { 0x0013FFFF, 0x01, 0x00, 0x14 },
+ Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x14 },
+ Package (0x04) { 0x0013FFFF, 0x03, 0x00, 0x14 },
+
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x13 },
+
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
+
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
+ })
+
+ Device (PEGG)
+ {
+ Name (_ADR, 0x00020000)
+ Name (_UID, 0x00)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
+ })
+ }
+
+ Device (PEX0)
+ {
+ Name (_ADR, 0x00030000)
+ Name (_UID, 0x00)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
+ })
+ }
+
+ Device (PEX1)
+ {
+ Name (_ADR, 0x00030001)
+ Name (_UID, 0x00)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
+ })
+ }
+
+ Device (PEX2)
+ {
+ Name (_ADR, 0x00030002)
+ Name (_UID, 0x00)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
+ })
+ }
+
+ Device (PEX3)
+ {
+ Name (_ADR, 0x00030003)
+ Name (_UID, 0x00)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
+ })
+ }
+
+ Device (PCI7)
+ {
+ Name (_ADR, 0x00130000)
+ Name (_UID, 0x00)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* IRQ17 */
+ })
+ }
+
+ Device (PCI8)
+ {
+ Name (_ADR, 0x00130001)
+ Name (_UID, 0x00)
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 }, /* PCI1 */
+ Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
+
+ Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 }, /* PCI2 */
+ Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
+ Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
+
+ Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 }, /* PCI3 */
+ Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x13 },
+ Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x10 },
+ Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x11 },
+
+ Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x13 }, /* PCI4 */
+ Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x10 },
+ Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x11 },
+ Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x12 },
+ })
+ }
+
+ Device (^PCIE)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x00)
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ Memory32Fixed(ReadOnly,
+ 0xE0000000,
+ 0x10000000,
+ )
+ })
+ Return (TMP)
+ }
+ }
+
+ Device (HPET) {
+ Name (_HID, EisaId ("PNP0103"))
+ Name (_UID, 0x00)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ Memory32Fixed(ReadOnly,
+ 0xFED00000,
+ 0x00000400,
+ )
+ IRQNoFlags () {0}
+ IRQNoFlags () {8}
+ })
+ Return (TMP)
+ }
+ }
+
+ Device (ISA) {
+ Name (_ADR, 0x00110000)
+
+ /* PS/2 keyboard (seems to be important for WinXP install) */
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 floppy controller */
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () {
+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+ IRQNoFlags () {6}
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
+ })
+ Return (BUF0)
+ }
+ }
+ }
+ }
+ }
+}
===================================================================
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 DDR400
+8 1 DDR333
+8 2 DDR266
+8 3 DDR200
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
+
+
===================================================================
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("ASUS M2V Mainboard")
+};
Add support for K8T890CF, VT8237A and ASUS M2V board. Needs crosschecking on VT8237R and VT8237S, since I had to touch some common codepaths like in src/southbridge/via/vt8237r/vt8237r_early_smbus.c Also because of the changed PCIe init code. Stupid issues that caused way too much (~1 day) headscratching until fixed: - I forgot to add the pci id in vt8237r_lpc.c: It was booting, but interrupts didn't work - I didn't have the 13.0 and 13.1 bridges in devicetree.cb: Linux saw the 13.0 bridge, but not the coreboot device scan. When enabling the 13.1 bridge, VGA init failed, since coreboot didn't see and initialize the bridge. Tested: - Linux boot (ACPI, APIC and LAPIC enabled) with acpi/mptables-enabled coreboot - HPET (detected and seems to work) - Serial port works - PCI slot irq routing works - PCIe slot irq routing works - MMCONFIG for extended pcie config space works - Booting from IDE HDD/CDROM works - Seabios won't boot from SATA, but both SATA controllers work in Linux - All 8 USB ports work FIXME: - PCIe doesn't get initialized on cold boot, only works when warm rebooting into Coreboot from Machine booted by AMI BIOS Someone with Datasheets needs to have a look I think - Onboard sound spews lots of "hda-intel: spurious response" messages and times out eventually. So for now we disable the bridge - VLINK settings works for me, but I don't have Datasheets Signed-Off-By: Tobias Diedrich <ranma+coreboot@tdiedrich.de> ---