Patchwork [6/7] ASUS M2V support (v2): Comments (unchanged)

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Submitter Tobias Diedrich
Date 2010-10-29 12:02:34
Message ID <20101029120234.GN31684@yumi.tdiedrich.de>
Download mbox | patch
Permalink /patch/2206/
State Superseded
Headers show

Comments

Tobias Diedrich - 2010-10-29 12:02:34
Minor comment changes, add pointer to PCIe bridge documentation.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>

---
Rudolf Marek - 2010-11-02 21:30:15
> -	/* ROM memory cycles go to LPC. */
> +	/* Only ROM memory cycles go to LPC. */

I think it should be,

 > +	/* Only memory ROM cycles go to LPC.  */

Because this bit is telling if all memory cycles should go to LPC or just those 
from ROM range. Please try to rephase that.

Thanks,
Rudolf

Patch

Index: src/southbridge/via/k8t890/k8t890_ctrl.c
===================================================================
--- src/southbridge/via/k8t890/k8t890_ctrl.c.orig	2010-10-29 13:47:38.000000000 +0200
+++ src/southbridge/via/k8t890/k8t890_ctrl.c	2010-10-29 13:47:57.000000000 +0200
@@ -154,7 +154,11 @@ 
 
 	pci_write_config8(dev, 0x47, 0x30);
 
-	/* VT8237R specific configuration  other SB are done in their own directories */
+	/*
+	 * VT8237R specific configuration,
+	 * other SB are done in their own directories:
+	 * VT8237A and VT8237S are handled in vt8237_ctrl.c
+	 */
 
 	device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
 					 PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
Index: src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig	2010-10-29 13:47:38.000000000 +0200
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c	2010-10-29 13:47:57.000000000 +0200
@@ -452,7 +452,7 @@ 
 	/* I/O recovery time, default IDE routing */
 	pci_write_config8(dev, 0x4c, 0x04);
 
-	/* ROM memory cycles go to LPC. */
+	/* Only ROM memory cycles go to LPC. */
 	pci_write_config8(dev, 0x59, 0x80);
 
 	/*
@@ -474,7 +474,7 @@ 
 	/* I/O recovery time, default IDE routing */
 	pci_write_config8(dev, 0x4c, 0x44);
 
-	/* ROM memory cycles go to LPC. */
+	/* Only ROM memory cycles go to LPC. */
 	pci_write_config8(dev, 0x59, 0x80);
 
 	/*
Index: src/southbridge/via/k8t890/k8t890_pcie.c
===================================================================
--- src/southbridge/via/k8t890/k8t890_pcie.c.orig	2010-10-29 13:48:04.000000000 +0200
+++ src/southbridge/via/k8t890/k8t890_pcie.c	2010-10-29 13:48:25.000000000 +0200
@@ -24,6 +24,12 @@ 
 #include <device/pci_ids.h>
 #include "k8t890.h"
 
+/*
+ * Note:
+ * The pcie bridges are similar to the VX800 ones documented at
+ * http://linux.via.com.tw/
+ */
+
 static void peg_init(struct device *dev)
 {
 	u8 reg;