From patchwork Fri Oct 29 20:41:07 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Remove incorrect IOAPIC lines from some mptable.c files Date: Fri, 29 Oct 2010 20:41:07 -0000 From: Uwe Hermann X-Patchwork-Id: 2210 Message-Id: <20101029204107.GC3256@greenwood> To: coreboot@coreboot.org See patch. Uwe. Acked-by: Jonathan Kollasch Remove incorrect IOAPIC lines from some mptable.c files. - via/epia-n/mptable.c - intel/eagleheights/mptable.c (commented out anyway) - asus/p2b-d/mptable.c - asus/p2b-ds/mptable.c Some files still incorrectly contain some smp_write_ioapic() lines from the original mptable utility target (Supermicro P4DPE), which has one IOAPIC in the southbridge (Intel ICH3-S), two IOAPICs contained in the first P64H2, and two more in the second P64H2, i.e. 5 IOAPICs in total. However, none of the boards where this chunk of code is present has multiple IOAPICs (and even if they had, the PCI devices where those are located would probably be different anyway), so drop the incorrect mptable.c contents. Also drop the lines from the mptable utility, so that future mptable.c files don't incorrectly inherit any of this stuff. Signed-off-by: Uwe Hermann Index: src/mainboard/via/epia-n/mptable.c =================================================================== --- src/mainboard/via/epia-n/mptable.c (Revision 6002) +++ src/mainboard/via/epia-n/mptable.c (Arbeitskopie) @@ -21,38 +21,7 @@ /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - { - device_t dev; - struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 3, 0x20, res->base); - } - } - dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 4, 0x20, res->base); - } - } - dev = dev_find_slot(4, PCI_DEVFN(0x1e,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 5, 0x20, res->base); - } - } - dev = dev_find_slot(4, PCI_DEVFN(0x1c,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 8, 0x20, res->base); - } - } - } + mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ Index: src/mainboard/intel/eagleheights/mptable.c =================================================================== --- src/mainboard/intel/eagleheights/mptable.c (Revision 6002) +++ src/mainboard/intel/eagleheights/mptable.c (Arbeitskopie) @@ -129,40 +129,7 @@ /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - /* - { - device_t dev; - struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 3, 0x20, res->base); - } - } - dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 4, 0x20, res->base); - } - } - dev = dev_find_slot(4, PCI_DEVFN(0x1e,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 5, 0x20, res->base); - } - } - dev = dev_find_slot(4, PCI_DEVFN(0x1c,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 8, 0x20, res->base); - } - } - } - */ + mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ Index: src/mainboard/asus/p2b-d/mptable.c =================================================================== --- src/mainboard/asus/p2b-d/mptable.c (Revision 6002) +++ src/mainboard/asus/p2b-d/mptable.c (Arbeitskopie) @@ -42,35 +42,6 @@ ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); - { - device_t dev; - struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1e, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 3, ioapic_ver, res->base); - } - dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 4, ioapic_ver, res->base); - } - dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 5, ioapic_ver, res->base); - } - dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 8, ioapic_ver, res->base); - } - } - /* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); Index: src/mainboard/asus/p2b-ds/mptable.c =================================================================== --- src/mainboard/asus/p2b-ds/mptable.c (Revision 6002) +++ src/mainboard/asus/p2b-ds/mptable.c (Arbeitskopie) @@ -41,36 +41,7 @@ /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - { - device_t dev; - struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1e, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 3, 0x20, res->base); - } - dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 4, 0x20, res->base); - } - dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 5, 0x20, res->base); - } - dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 8, 0x20, res->base); - } - } - mptable_add_isa_interrupts(mc, 0x1, 0x2, 0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, Index: util/mptable/mptable.c =================================================================== --- util/mptable/mptable.c (Revision 6002) +++ util/mptable/mptable.c (Arbeitskopie) @@ -320,9 +320,7 @@ }; char *postamble[] = { -" /* There is no extension information... */", -"", -" /* Compute the checksums */", +" /* Compute the checksums. */", " mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);", " mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);", " printk(BIOS_DEBUG, \"Wrote the mp table end at: %p - %p\\n\",", @@ -341,38 +339,7 @@ char *ioapic_code[] = { " smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);", -" {", -" device_t dev;", -" struct resource *res;", -" dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));", -" if (dev) {", -" res = find_resource(dev, PCI_BASE_ADDRESS_0);", -" if (res) {", -" smp_write_ioapic(mc, 3, 0x20, res->base);", -" }", -" }", -" dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));", -" if (dev) {", -" res = find_resource(dev, PCI_BASE_ADDRESS_0);", -" if (res) {", -" smp_write_ioapic(mc, 4, 0x20, res->base);", -" }", -" }", -" dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));", -" if (dev) {", -" res = find_resource(dev, PCI_BASE_ADDRESS_0);", -" if (res) {", -" smp_write_ioapic(mc, 5, 0x20, res->base);", -" }", -" }", -" dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));", -" if (dev) {", -" res = find_resource(dev, PCI_BASE_ADDRESS_0);", -" if (res) {", -" smp_write_ioapic(mc, 8, 0x20, res->base);", -" }", -" }", -" }", +" /* TODO: If you have multiple IOAPICs, add them here. */", 0 }; static void