Comments
Patch
===================================================================
@@ -58,7 +58,7 @@
res->limit = res->base + res->size - 1;
res->align = 8;
res->gran = 8;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
/* Add an MMCONFIG resource. */
@@ -67,7 +67,7 @@
res->align = log2(res->size);
res->gran = log2(res->size);
res->limit = 0xffffffff; /* 4G */
- res->flags = IORESOURCE_MEM;
+ res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE;
}
static void traf_ctrl_enable_generic(struct device *dev)
===================================================================
@@ -566,7 +566,15 @@
res->limit = 0xffffffffUL;
res->align = 8;
res->gran = 8;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
+ IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ /* Fixed flashrom resource */
+ res = new_resource(dev, 4);
+ res->base = 0xffc00000UL;
+ res->size = 0x00400000UL; /* 4MB */
+ res->limit = 0xffffffffUL;
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
res = new_resource(dev, 1);
Ranges unavailable for PCI BARs should be marked as reserved in the E820 memory map, in case the OS wants to change the BARs. This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF resource flags to do this. I also added a new resource for the mapped bios rom area just below 4GB. I'm not sure if the choice for the index parameter of new_resource() is correct though. Note that the bios rom decode is enabled in src/southbridge/via/vt8237r/vt8237r_early_smbus.c for the whole 4MB area (even though the comment says 1MB). Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> ---