Patchwork EPIA halting after vt8601 init

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Submitter Uwe Hermann
Date 2010-11-04 00:16:47
Message ID <20101104001646.GS3256@greenwood>
Download mbox | patch
Permalink /patch/2242/
State Superseded
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Comments

Uwe Hermann - 2010-11-04 00:16:47
On Wed, Nov 03, 2010 at 03:00:54PM -0600, Myles Watson wrote:
> > Is this rom structure reasonable (missing fallback/romstage?):
> It's fine.  The romstage (boot block) isn't part of CBFS.
> 
> 
> > Loading stage image.
> > Check CBFS header at <hangs here>
> Normally a hang here means that the whole ROM isn't mapped, so trying
> to read from the top of the ROM hangs, even though the bootblock
> accesses work fine.

Yup, sounds like that's the problem. Here's a quick patch to fix it
by adding a rom_enable() function (and converting VT8231 to
TINYBOOTBLOCK) while I'm at it. The only problem: It won't compile ;)

    ROMCC      romstage.inc
mtrr.h:73.42: 
non const static variables not supported
make: *** [build/mainboard/via/epia/romstage.inc] Error 1

No time to investigate right now, if someone else sees the problem,
please feel free to fix and commit. Probably just some missing
"#if defined(ROMCC)" or the like.


Uwe.

Patch

ROM enable function for VIA VT8231, convert it to TINYBOOTBLOCK.

 - Adding the ROM enable function is required (very early) since CBFS,
   otherwise the boot process will hang.

 - The "Map 4MB of FLASH into the address space" code in vt8231_lpc.c looks
   incorrect, that register does something completely different according
   to the VT8231 datasheet (probably copypaste from another VIA SB).
   The new enable_rom() should do the right thing, so drop the old code.
 
 - While we're at it, convert the VT8231 to TINYBOOTBLOCK, too.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>

Index: src/southbridge/via/vt8231/bootblock.c
===================================================================
--- src/southbridge/via/vt8231/bootblock.c	(Revision 0)
+++ src/southbridge/via/vt8231/bootblock.c	(Revision 0)
@@ -0,0 +1,26 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "southbridge/via/vt8231/vt8231_enable_rom.c"
+
+static void bootblock_southbridge_init(void)
+{
+	vt8231_enable_rom();
+}
Index: src/southbridge/via/vt8231/Kconfig
===================================================================
--- src/southbridge/via/vt8231/Kconfig	(Revision 6016)
+++ src/southbridge/via/vt8231/Kconfig	(Arbeitskopie)
@@ -20,3 +20,10 @@ 
 config SOUTHBRIDGE_VIA_VT8231
 	bool
 	select HAVE_DEBUG_SMBUS
+	select TINY_BOOTBLOCK
+
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/via/vt8231/bootblock.c"
+	depends on SOUTHBRIDGE_VIA_VT8231
+
Index: src/southbridge/via/vt8231/vt8231_lpc.c
===================================================================
--- src/southbridge/via/vt8231/vt8231_lpc.c	(Revision 6016)
+++ src/southbridge/via/vt8231/vt8231_lpc.c	(Arbeitskopie)
@@ -61,9 +61,6 @@ 
 	enables |= 0x80;
 	pci_write_config8(dev, 0x6C, enables);
 
-	// Map 4MB of FLASH into the address space
-	pci_write_config8(dev, 0x41, 0x7f);
-
 	// Set bit 6 of 0x40, because Award does it (IO recovery time)
 	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
 	// interrupts can be properly marked as level triggered.
Index: src/southbridge/via/vt8231/vt8231_enable_rom.c
===================================================================
--- src/southbridge/via/vt8231/vt8231_enable_rom.c	(Revision 0)
+++ src/southbridge/via/vt8231/vt8231_enable_rom.c	(Revision 0)
@@ -0,0 +1,47 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+
+static void vt8231_enable_rom(void)
+{
+	device_t dev;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+	                               PCI_DEVICE_ID_VIA_8231), 0);
+
+	/*
+	 * ROM decode control register (0x43):
+	 *
+	 * Bit  Decode range
+	 * -----------------
+	 * 7	0xFFFE0000-0xFFFEFFFF
+	 * 6	0xFFF80000-0xFFFDFFFF
+	 * 5	0xFFF00000-0xFFF7FFFF
+	 * 4	0x000E0000-0x000EFFFF
+	 * 3	0x000D8000-0x000DFFFF
+	 * 2	0x000D0000-0x000D7FFF
+	 * 1	0x000C8000-0x000CFFFF
+	 * 0	0x000C0000-0x000C7FFF
+	 */
+	pci_write_config8(dev, 0x43, (1 << 7) | (1 << 6) | (1 << 5));
+}