Patchwork [superiotool] Fix VID / SPI registers for F71889

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Submitter Neo The User
Date 2010-11-04 15:17:40
Message ID <596879.86361.qm@web114117.mail.gq1.yahoo.com>
Download mbox | patch
Permalink /patch/2248/
State Accepted
Headers show

Comments

Neo The User - 2010-11-04 15:17:40
Hi, The SPI should be on 0x8, not 0x7, as that is the VID. I double checked the datasheet and came across this while working on the coreboot port for my board. This is a follow-up for the initial F71889 support for superiotool.

Patch

Index: fintek.c
===================================================================
--- fintek.c	(revision 6017)
+++ fintek.c	(working copy)
@@ -158,6 +158,50 @@ 
 			{0x30,0xf0,0xf1,0xf4,0xf5,EOT},
 			{0x00,0x00,0x01,0x06,0x1c,EOT}},
 		{EOT}}},
+        {0x2307, "F71889", {
+                /* We assume reserved bits are read as 0. */
+                {NOLDN, NULL,
+                        {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,
+                         0x2b,0x2c,0x2d,EOT},
+                        {0x05,0x41,0x19,0x34,0x00,0x00,0x00,0x00,0x00,0x00,
+                         0x00,0x08,0x08,EOT}},
+                {0x0, "Floppy",
+                        {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT},
+                        {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}},
+                {0x1, "COM1",
+                        {0x30,0x60,0x61,0x70,0xf0,EOT},
+                        {0x01,0x03,0xf8,0x04,0x00,EOT}},
+                {0x2, "COM2",
+                        {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
+                        {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}},
+                {0x3, "Parallel port",
+                        {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
+                        {0x01,0x03,0x78,0x07,0x03,0x42,EOT}},
+                {0x4, "Hardware monitor",
+                        {0x30,0x60,0x61,0x70,EOT},
+                        {0x01,0x02,0x95,0x00,EOT}},
+                {0x5, "Keyboard",
+                        {0x30,0x60,0x61,0x70,0x72,0xf0,EOT},
+                        {0x01,0x00,0x60,0x00,0x00,0x83,EOT}},
+                {0x6, "GPIO",
+                        {0x70,0xe0,0xe1,0xe2,0xe3,0xd0,0xd1,0xd2,0xd3,0xc0,
+                         0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3,0xf0,0xf1,0xf2,
+                         0xf3,EOT},
+                        {0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,
+                         0x0f,NANA,0x00,0x00,0x0f,NANA,0x00,0x00,0xff,NANA,
+                         0x00,EOT}},
+                {0x7, "VID",
+                        {0x30,0x60,0x61,EOT},
+                        {0x00,0x00,0x00,EOT}},
+                {0x8, "SPI",
+                        {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,
+                         0xfb,0xfc,0xfd,0xfe,0xff,EOT},
+                        {0x10,0x04,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                         0x00,0x00,0x00,0x00,0x00,EOT}},
+                {0xa, "PME, ACPI",
+                        {0x30,0xf0,0xf1,0xf4,0xf5,EOT},
+                        {0x00,0x00,0x01,0x06,0x1c,EOT}},
+                {EOT}}},
 	{0x0604, "F71805F/FG", {
 		/* We assume reserved bits are read as 0. */
 		{NOLDN, NULL,