Patchwork : Entry key of fintek superio is 8787 instead of 87

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Submitter Bao, Zheng
Date 2010-11-05 07:19:08
Message ID <DD1CC71B621B004FA76856E5129D6B1704411ABF@sbjgexmb1.amd.com>
Download mbox | patch
Permalink /patch/2253/
State Accepted
Commit r6025
Headers show

Comments

Bao, Zheng - 2010-11-05 07:19:08
According to the description in datasheet of f71889,

"To enable configuration, the entry key 0x87 must be written to
the index port"

"
 -o 4e 87
 -o 4e 87	(enable configuration)
 -o 4e aa	(disable configuration)
"
This piece of text appears in most of the datasheet of fintek superio.
It doesnt say it quite clear, but it seems that the 0x87 should
be written twice. I tried on f81865, which is not in the coreboot tree
yet. If the 0x87 is only written once, you can only R/W the index/data
port once. All the subsequent RW will fail. Writing twice will be ok.

Plus, in the superiotool, the function
enter_conf_mode_winbond_fintek_ite_8787
also write 8787.

The fintek superio chips seem to enable the UART automatically when the
power is on. So I didnt find it failed to access.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
According to the description in datasheet of f71889,

"To enable configuration, the entry key 0x87 must be written to
the index port"

"
 -o 4e 87
 -o 4e 87	(enable configuration)
 -o 4e aa	(disable configuration)
"
This piece of text appears in most of the datasheet of fintek superio.
It doesnt say it quite clear, but it seems that the 0x87 should
be written twice. I tried on f81865, which is not in the coreboot tree
yet. If the 0x87 is only written once, you can only R/W the index/data
port once. All the subsequent RW will fail. Writing twice will be ok.

Plus, in the superiotool, the function enter_conf_mode_winbond_fintek_ite_8787
also write 8787.

The fintek superio chips seem to enable the UART automatically when the
power is on. So I didnt find it failed to access.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Stefan Reinauer - 2010-11-05 07:51:40
On 11/5/10 12:19 AM, Bao, Zheng wrote:
> According to the description in datasheet of f71889,
>
> "To enable configuration, the entry key 0x87 must be written to
> the index port"
>
> "
>  -o 4e 87
>  -o 4e 87	(enable configuration)
>  -o 4e aa	(disable configuration)
> "
> This piece of text appears in most of the datasheet of fintek superio.
> It doesnt say it quite clear, but it seems that the 0x87 should
> be written twice. I tried on f81865, which is not in the coreboot tree
> yet. If the 0x87 is only written once, you can only R/W the index/data
> port once. All the subsequent RW will fail. Writing twice will be ok.
>
> Plus, in the superiotool, the function
> enter_conf_mode_winbond_fintek_ite_8787
> also write 8787.
>
> The fintek superio chips seem to enable the UART automatically when the
> power is on. So I didnt find it failed to access.
>
> Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>

Stefan

Patch

Index: src/superio/fintek/f71805f/f71805f_early_serial.c
===================================================================
--- src/superio/fintek/f71805f/f71805f_early_serial.c	(revision 6024)
+++ src/superio/fintek/f71805f/f71805f_early_serial.c	(working copy)
@@ -27,6 +27,7 @@ 
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
+	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)
Index: src/superio/fintek/f71859/f71859_early_serial.c
===================================================================
--- src/superio/fintek/f71859/f71859_early_serial.c	(revision 6024)
+++ src/superio/fintek/f71859/f71859_early_serial.c	(working copy)
@@ -27,6 +27,7 @@ 
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
+	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)
Index: src/superio/fintek/f71889/f71889_early_serial.c
===================================================================
--- src/superio/fintek/f71889/f71889_early_serial.c	(revision 6024)
+++ src/superio/fintek/f71889/f71889_early_serial.c	(working copy)
@@ -26,6 +26,7 @@ 
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
+	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)
Index: src/superio/fintek/f71863fg/f71863fg_early_serial.c
===================================================================
--- src/superio/fintek/f71863fg/f71863fg_early_serial.c	(revision 6024)
+++ src/superio/fintek/f71863fg/f71863fg_early_serial.c	(working copy)
@@ -27,6 +27,7 @@ 
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
+	outb(0x87, port);
 }
 
 static void pnp_exit_conf_state(device_t dev)