Patchwork V-link optimization on K8M890/VT8237S

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Submitter Rudolf Marek
Date 2009-08-30 15:34:16
Message ID <4A9A9BF8.7070009@assembler.cz>
Download mbox | patch
Permalink /patch/230/
State Accepted
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Comments

Rudolf Marek - 2009-08-30 15:34:16
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Hi all,

As more users of Asus M2V-MX SE emerged. Here is long pending patch I wanted to
write. It boots the SB/NB V-link performance to full duplex 533MB/s. (in fact x2
for FDX)

The default was 266MB/s but half duplex only. If you encourage any stability
issues we need to look into fine tuning the bus. The values are VIA recommended.

Rudolf
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Stefan Reinauer - 2009-08-31 14:49:21
Rudolf Marek wrote:
> Hi all,
>
> As more users of Asus M2V-MX SE emerged. Here is long pending patch I
> wanted to
> write. It boots the SB/NB V-link performance to full duplex 533MB/s.
> (in fact x2
> for FDX)
>
> The default was 266MB/s but half duplex only. If you encourage any
> stability
> issues we need to look into fine tuning the bus. The values are VIA
> recommended.
>
> Rudolf

Is there some way to find out the "correct" maximum speed, as on Hyper
Transport?

Anyways

Acked-by: Stefan Reinauer <stepan@coresystems.de>
Rudolf Marek - 2009-09-01 15:29:43
> Is there some way to find out the "correct" maximum speed, as on Hyper
> Transport?

Yes there is but it is fixed for the known SB/NB combinations so we don't need 
this yet. Also for each mode a set of fine tunes is necessary.

> Acked-by: Stefan Reinauer <stepan@coresystems.de>

Ok thanks.

I forgot to Signed-off-by: Rudolf Marek <r.marek@assembler.cz>

Committed revision 4625.

Thanks,
Rudolf

Patch

Index: src/southbridge/via/vt8237r/vt8237_ctrl.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237_ctrl.c	(revision 4566)
+++ src/southbridge/via/vt8237r/vt8237_ctrl.c	(working copy)
@@ -94,6 +94,9 @@ 
  * V-Link CKG Control				 0xb0  0x05  0x05  0x06  0x03
  * V-Link CKG Control				 0xb1  0x05  0x05  0x01  0x03
  */
+
+/* we setup 533MB/s mode full duplex */
+
 static void vt8237s_vlink_init(struct device *dev)
 {
 	u8 reg;
@@ -114,24 +117,47 @@ 
 	 * and VT8251) a different init code is required.
 	 */
 
+	/* disable auto disconnect */
+	reg = pci_read_config8(devfun7, 0x42);
+	reg &= ~0x4;
+	pci_write_config8(devfun7, 0x42, reg);
+
+	/* NB part setup */
 	pci_write_config8(devfun7, 0xb5, 0x66);
 	pci_write_config8(devfun7, 0xb6, 0x66);
-	pci_write_config8(devfun7, 0xb7, 0x65);
+	pci_write_config8(devfun7, 0xb7, 0x64);
 
 	reg = pci_read_config8(devfun7, 0xb4);
 	reg |= 0x1;
+	reg &= ~0x10;
 	pci_write_config8(devfun7, 0xb4, reg);
 
-	pci_write_config8(dev, 0xb9, 0x68);
+	pci_write_config8(devfun7, 0xb0, 0x6);
+	pci_write_config8(devfun7, 0xb1, 0x1);
+
+	/* SB part setup */
+	pci_write_config8(dev, 0xb7, 0x60);
+	pci_write_config8(dev, 0xb9, 0x88);
 	pci_write_config8(dev, 0xba, 0x88);
 	pci_write_config8(dev, 0xbb, 0x89);
 
 	reg = pci_read_config8(dev, 0xbd);
 	reg |= 0x3;
+	reg &= ~0x4;
 	pci_write_config8(dev, 0xbd, reg);
 
-	/* Program V-link 8X 8bit full duplex, parity disabled. FIXME. */
-	pci_write_config8(dev, 0x48, 0x13);
+	reg = pci_read_config8(dev, 0xbc);
+	reg &= ~0x7;
+	pci_write_config8(dev, 0xbc, reg);
+
+	/* Program V-link 8X 8bit full duplex, parity enabled.  */
+	pci_write_config8(dev, 0x48, 0x23 | 0x80);
+
+	/* enable auto disconnect, for STPGNT and HALT */
+	reg = pci_read_config8(devfun7, 0x42);
+	reg |= 0x7;
+	pci_write_config8(devfun7, 0x42, reg);
+
 }
 
 static void ctrl_enable(struct device *dev)
@@ -158,8 +184,7 @@ 
 	device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
 					 PCI_DEVICE_ID_VIA_VT8237S_LPC, 0);
 	if (devsb) {
-		/* FIXME: Skip v-link setup for now. */
-//              vt8237s_vlink_init(dev);
+		vt8237s_vlink_init(dev);
 	}
 
 	/* Configure PCI1 and copy mirror registers from D0F3. */