Patchwork [v2] ck804 PCIe lane configuration in kconfig

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Submitter Jonathan A. Kollasch
Date 2010-11-21 20:31:55
Message ID <20101121203155.GG9233@tarantulon.kollasch.net>
Download mbox | patch
Permalink /patch/2341/
State Accepted
Headers show

Comments

Jonathan A. Kollasch - 2010-11-21 20:31:55
Move CK804_PCI_E_X and CK804B_PCI_E_X defines (which have been 4 by
default on all boards) into Kconfig.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
---
Uwe Hermann - 2010-11-21 21:38:06
On Sun, Nov 21, 2010 at 08:31:55PM +0000, Jonathan A. Kollasch wrote:
> -#define CK804_CHIP_REV 3

Hm, why remove CK804_CHIP_REV? I have no idea if or how that's supposed
to be used etc., though. Here's a quick grep:

southbridge/nvidia/ck804/ck804_early_setup_car.c:#define CK804_CHIP_REV 3
southbridge/nvidia/ck804/ck804_early_setup.c:#define CK804_CHIP_REV 3
southbridge/nvidia/ck804/ck804_lpc.c:#define CK804_CHIP_REV 2
southbridge/nvidia/ck804/ck804_lpc.c:#if CK804_CHIP_REV==1
southbridge/nvidia/ck804/ck804_lpc.c:#if CK804_CHIP_REV == 1

Maybe we should keep the #define until we know more.


The rest of the patch looks ok.

Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


Uwe.
Jonathan A. Kollasch - 2010-11-21 22:56:48
On Sun, Nov 21, 2010 at 10:38:06PM +0100, Uwe Hermann wrote:
> On Sun, Nov 21, 2010 at 08:31:55PM +0000, Jonathan A. Kollasch wrote:
> > -#define CK804_CHIP_REV 3
> 
> Hm, why remove CK804_CHIP_REV? I have no idea if or how that's supposed

> Maybe we should keep the #define until we know more.
> 

Kept.

r6109.

Patch

Index: src/southbridge/nvidia/ck804/Kconfig
===================================================================
--- src/southbridge/nvidia/ck804/Kconfig	(revision 6107)
+++ src/southbridge/nvidia/ck804/Kconfig	(working copy)
@@ -5,30 +5,42 @@ 
 	select IOAPIC
 	select TINY_BOOTBLOCK
 
+if SOUTHBRIDGE_NVIDIA_CK804
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string  
-	default "southbridge/nvidia/ck804/bootblock.c" if SOUTHBRIDGE_NVIDIA_CK804
+	default "southbridge/nvidia/ck804/bootblock.c"
 
 config ID_SECTION_OFFSET
 	hex
-	default 0x80 if SOUTHBRIDGE_NVIDIA_CK804
+	default 0x80
 
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_NVIDIA_CK804
+	default 0xfef00000
 
 config EHCI_DEBUG_OFFSET
 	hex
-	default 0x98 if SOUTHBRIDGE_NVIDIA_CK804
+	default 0x98
 
 config CK804_USE_NIC
 	bool
-	default n if SOUTHBRIDGE_NVIDIA_CK804
+	default n
 
 config CK804_USE_ACI
 	bool
-	default n if SOUTHBRIDGE_NVIDIA_CK804
+	default n
 
+config CK804_PCI_E_X
+	int
+	default 4
+
+config CK804B_PCI_E_X
+	int
+	default 4
+
 config CK804_NUM
 	int
-	default 1 if SOUTHBRIDGE_NVIDIA_CK804
+	default 1
+
+endif
Index: src/southbridge/nvidia/ck804/ck804_early_setup.c
===================================================================
--- src/southbridge/nvidia/ck804/ck804_early_setup.c	(revision 6107)
+++ src/southbridge/nvidia/ck804/ck804_early_setup.c	(working copy)
@@ -56,30 +56,24 @@ 
 #define SYSCTRL_REG_POS 0x64
 
 /*
+ * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X.
+ * Apparently some sort of lane configuration.
+ *
  *	16 1 1 2 :0
  *	 8 8 2 2 :1
  *	 8 8 4   :2
  *	 8 4 4 4 :3
  *	16 4     :4
-*/
+ */
 
-#ifndef CK804_PCI_E_X
-#define CK804_PCI_E_X 4
-#endif
-
 #if CONFIG_CK804_NUM > 1
 #define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000)
 #define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000)
 #ifndef CK804B_BUSN
 #define CK804B_BUSN 0x80
 #endif
-#ifndef CK804B_PCI_E_X
-#define CK804B_PCI_E_X 4
 #endif
-#endif
 
-#define CK804_CHIP_REV 3
-
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
 #else
@@ -258,9 +252,9 @@ 
 
 	RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
 
-	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
+	RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8),
 #if CONFIG_CK804_NUM > 1
-	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
+	RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8),
 #endif
 
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
Index: src/southbridge/nvidia/ck804/ck804_early_setup_car.c
===================================================================
--- src/southbridge/nvidia/ck804/ck804_early_setup_car.c	(revision 6107)
+++ src/southbridge/nvidia/ck804/ck804_early_setup_car.c	(working copy)
@@ -54,23 +54,16 @@ 
 #define SYSCTRL_REG_POS 0x64
 
 /*
+ * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X.
+ * Apparently some sort of lane configuration.
+ *
  *	16 1 1 2 :0
  *	 8 8 2 2 :1
  *	 8 8 4   :2
  *	 8 4 4 4 :3
  *	16 4     :4
-*/
+ */
 
-#ifndef CK804_PCI_E_X
-#define CK804_PCI_E_X 4
-#endif
-
-#ifndef CK804B_PCI_E_X
-#define CK804B_PCI_E_X 4
-#endif
-
-#define CK804_CHIP_REV 3
-
 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
 #else
@@ -199,7 +192,7 @@ 
 
 		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
 
-		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8),
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8),
 
 //SYSCTRL
 		RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
@@ -275,7 +268,7 @@ 
 /* This line doesn't exist in the non-CAR version. */
 		RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
 
-		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8),
+		RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8),
 
 #if CONFIG_CK804_USE_NIC
 		RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,