===================================================================
@@ -0,0 +1,164 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Based on src/southbridge/via/vt8237r/vt8237_fadt.c */
+
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <device/pci.h>
+/* PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI */
+#include <device/pci_ids.h>
+#include "i82371eb.h" /* PM_IO_BASE, PMCNTRL */
+
+/**
+ * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
+ */
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ device_t dev;
+
+ /* Power management controller */
+ dev = dev_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); /* pci_ids.h */
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = 244;
+ header->revision = 1;
+ memcpy(header->oem_id, "COREBO", 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 42;
+
+// fadt->firmware_ctrl = (u32)facs;
+ fadt->dsdt = (u32)dsdt;
+ fadt->preferred_pm_profile = 0;
+ fadt->sci_int = 9;
+ fadt->smi_cmd = 0xb2; // smi command port ?
+ fadt->acpi_enable = 0xa1;
+ fadt->acpi_disable = 0xa0;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0x0;
+
+ fadt->pm1a_evt_blk = PM_IO_BASE; /* PM_IO_BASE = 0xe400 */
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = PM_IO_BASE + PMCNTRL; /* PMCNTRL = 0x4 */
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = 0x0;
+ fadt->pm_tmr_blk = PM_IO_BASE + PMTMR; /* PMTMR = 0x8 */
+ fadt->gpe0_blk = PM_IO_BASE + GPSTS; /* GPSTS = 0xc */
+ fadt->gpe1_blk = 0x0;
+ fadt->gpe1_base = 0;
+ fadt->gpe1_blk_len = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 0;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 4;
+
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 0x5a;
+ fadt->p_lvl3_lat = 0x0384;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0x0d;
+ fadt->mon_alrm = 0x0;
+ fadt->century = 0x0;
+ fadt->iapc_boot_arch = 0x0;
+ fadt->flags = 0xa5;
+
+ fadt->reset_reg.space_id = 0;
+ fadt->reset_reg.bit_width = 0;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0x0;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 0;
+ fadt->x_firmware_ctl_l = (u32)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (u32)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
+}
===================================================================
@@ -2,6 +2,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -28,3 +29,6 @@
romstage-y += i82371eb_early_pm.c
romstage-y += i82371eb_early_smbus.c
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += i82371eb_smi.c
+#obj-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += i82371eb_smihandler.c
===================================================================
@@ -2,6 +2,8 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -59,28 +61,59 @@
#define SMBHSTCFG 0xd2 /* SMBus host configuration */
/* Power management (ACPI) */
+#define GLBCTL 0x28 /* Global control register */
+#define GPSTS 0x0c /* General Purpose Status */
#define PMBA 0x40 /* Power management base address */
+#define PMCNTRL 0x04 /* Power Management Control */
+#define PM_IO_BASE 0xe400
+#define PMIOSE (1 << 0)/* PM I/O Space Enable */
#define PMREGMISC 0x80 /* Miscellaneous power management */
+#define PMTMR 0x08 /* Power Management Timer */
-#define PM_IO_BASE 0xe400
+/* Device resources */
+#define DEVRESA 0x5c /* Device Resource A */
+#define DEVRESB 0x60 /* Device Resource B */
+#define DEVRESC 0x64 /* Device Resource C */
+#define DEVRESD 0x50 /* Device Resource D */
+#define DEVRESE 0x68 /* Device Resource E */
+#define DEVRESF 0x6c /* Device Resource F */
+#define DEVRESG 0x70 /* Device Resource G */
+#define DEVRESH 0x74 /* Device Resource H */
+#define DEVRESI 0x78 /* Device Resource I */
+#define DEVRESJ 0x7c /* Device Resource J */
+/* Device activity */
+#define DEVACTA 0x54 /* Device Activity A */
+#define DEVACTB 0x58 /* Device Activity B */
+
/* Bit definitions */
+#define DTE0 (1 << 3) /* DMA Timing Enable Only, drive 0 */
+#define DTE1 (1 << 7) /* DMA Timing Enable Only, drive 1 */
+#define EIO (0 << 0) /* Select EIO */
#define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */
#define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */
+#define ISA (1 << 0) /* Select ISA */
+#define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */
#define LOWER_BIOS_ENABLE (1 << 6) /* Lower BIOS Enable */
-#define WRITE_PROTECT_ENABLE (1 << 2) /* Write Protect Enable */
-#define SRST (1 << 1) /* System Reset */
+#define PSDE0 (1 << 0) /* Primary Drive 0 UDMA/33 */
+#define PSDE1 (1 << 1) /* Primary Drive 1 UDMA/33 */
#define RCPU (1 << 2) /* Reset CPU */
#define SMB_HST_EN (1 << 0) /* Host Interface Enable */
-#define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */
-#define DTE0 (1 << 3) /* DMA Timing Enable Only, drive 0 */
-#define DTE1 (1 << 7) /* DMA Timing Enable Only, drive 1 */
-#define PSDE0 (1 << 0) /* Primary Drive 0 UDMA/33 */
-#define PSDE1 (1 << 1) /* Primary Drive 1 UDMA/33 */
+#define SUS_EN (1 << 13) /* Suspend Enable (SLP_EN) */
+#define SRST (1 << 1) /* System Reset */
#define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */
#define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */
-#define ISA (1 << 0) /* Select ISA */
-#define EIO (0 << 0) /* Select EIO */
-#define PMIOSE (1 << 0) /* PM I/O Space Enable */
+#define WRITE_PROTECT_ENABLE (1 << 2) /* Write Protect Enable */
+/* SMI/SMM */
+#define SMI_EN (1 << 0) /* Enable SMI# generation */
+#define EXTSMI_STS (1 << 10) /* This is for i82371eb_smi.c:reset_smi_status() */
+#define EOS (1 << 16) /* Enable End of SMI */
+
+/* IRQ routing */
+#define PIRQA 0xB
+#define PIRQB 0xB
+#define PIRQC 0xB
+#define PIRQD 0xB
+
#endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */
===================================================================
@@ -27,8 +27,6 @@
#include "i82371eb.h"
#include "i82371eb_smbus.h"
-#define SMBUS_IO_BASE 0x0f00
-
int smbus_read_byte(u8 device, u8 address);
void enable_smbus(void)
===================================================================
@@ -0,0 +1,163 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+#include <device/pci_def.h>
+
+//#include "i82371eb.h"
+
+//static u16 reset_pm1_status(void)
+//{
+ // Not implemented
+// return 0;
+//}
+
+//static void dump_pm1_status(u16 pm1_sts)
+//{
+ // Not implemented
+//}
+
+static u32 reset_smi_status(void)
+{
+ // Not implemented
+ return 0;
+}
+
+static void dump_smi_status(u32 smi_sts)
+{
+ // Not implemented
+}
+
+//static u32 reset_gpe0_status(void)
+//{
+ // Not implemented
+// return 0;
+//}
+
+//static void dump_gpe0_status(u32 gpe0_sts)
+//{
+ // Not implemented
+//}
+
+//static u32 reset_tco_status(void)
+//{
+ // Not implemented
+// return 0;
+//}
+
+//static void dump_tco_status(u32 tco_sts)
+//{
+ // Not implemented
+//}
+
+int southbridge_io_trap_handler(int smif)
+{
+ // Not implemented
+ return 0;
+}
+
+void southbridge_smi_set_eos(void)
+{
+ // Not implemented
+}
+
+//static void busmaster_disable_on_bus(int bus)
+//{
+ // Not implemented
+//}
+
+//static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
+//{
+ // Not implemented
+//}
+
+//static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
+//{
+ // Not implemented
+//}
+
+//static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
+//{
+ // Not implemented
+// u16 pm1_sts;
+
+// pm1_sts = reset_pm1_status();
+// dump_pm1_status(pm1_sts);
+//}
+
+//static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
+//{
+ // Not implemented
+// u32 gpe0_sts;
+
+// gpe0_sts = reset_gpe0_status();
+// dump_gpe0_status(gpe0_sts);
+//}
+
+//static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
+//{
+ // Not implemented
+//}
+
+//static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
+//{
+ // Not implemented
+//}
+
+//static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
+//{
+ // Not implemented
+// u32 tco_sts;
+
+// tco_sts = reset_tco_status();
+
+// if (!tco_sts) {
+// dump_tco_status(tco_sts);
+// }
+//}
+
+//static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
+//{
+ // Not implemented
+//}
+
+//static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
+//{
+ // Not implemented
+//}
+
+void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
+{
+ // Not implemented
+ int dump = 0;
+ u32 smi_sts;
+
+ smi_sts = reset_smi_status();
+
+ if (dump) {
+ dump_smi_status(smi_sts);
+ }
+}
+
===================================================================
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+#include <string.h>
+
+#include "i82371eb.h"
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+static u16 reset_pm1_status(void)
+{
+ // Not implemented
+ return 0;
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+static void dump_pm1_status(u16 pm1_sts)
+{
+ // Not implemented
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+static u32 reset_smi_status(void)
+{
+ // Not implemented
+ return 0;
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+static void dump_smi_status(u32 smi_sts)
+{
+ // Not implemented
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+static u32 reset_gpe0_status(void)
+{
+ // Not implemented
+ return 0;
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+static void dump_gpe0_status(u32 gpe0_sts)
+{
+ // Not implemented
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+static u16 reset_alt_gp_smi_status(void)
+{
+ // Not implemented
+ return 0;
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
+{
+ // Not implemented
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+static u32 reset_tco_status(void)
+{
+ // Not implemented
+ return 0;
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+static void dump_tco_status(u32 tco_sts)
+{
+ // Not implemented
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+static void smi_set_eos(void)
+{
+ // Not implemented
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+static void smm_relocate(void)
+{
+ // Not implemented
+ dump_smi_status(reset_smi_status());
+ dump_pm1_status(reset_pm1_status());
+ dump_gpe0_status(reset_gpe0_status());
+ dump_alt_gp_smi_status(reset_alt_gp_smi_status());
+ dump_tco_status(reset_tco_status());
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+static void smm_install(void)
+{
+ // Not implemented
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+void smm_init(void)
+{
+ // Not implemented
+ smm_install();
+ smm_relocate();
+ smi_set_eos();
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+void smm_lock(void)
+{
+ // Not implemented
+}
+
+// copied from src/southbridge/intel/i82801dx/i82801dx_smi.c
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
+{
+ // Not implemented
+}
===================================================================
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,6 +19,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/io.h> // include fix for inb() / outw()
+#include <console/console.h> // include fix for printk()
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
@@ -26,7 +29,65 @@
#include "i82371eb.h"
#include "i82371eb_smbus.h"
-/* TODO: Needed later? */
+/* Table format: register, bitmask, value. */
+static const u8 register_values[] = {
+ /* DEVRESE - Device Resource E
+ * 0x68 - 0x6A
+ *
+ * [23:21] Reserved
+ * [20:20] Device 12 I/O Monitor Enable (IO_EN_DEV12)
+ * 0 = Enable PCI bus decode for accesses to the I/O address
+ * range selected by the IBASE_DEV12 and IMASK_DEV12 fields
+ * 1 = Disable
+ * [19:16] Device 12 I/O Decode Mask (IMASK_DEV12)
+ * Specifies the 4-bit I/O base address mask used to determine
+ * the IO address range size for device 12 accesses.
+ * IMASK_DEV12 (bits[19:16]) correspond to AD[3:0]. A '1' in a
+ * bit position indicates that the corresponding address bit is
+ * masked (i.e. ignored) when performing the decode. Note that
+ * programming these bits to certain patterns (such as '1001')
+ * results in a split address range.
+ * [15:00] Device 12 I/O Decode Base Address (IBASE_DEV12)
+ * Specifies the 16-bit I/O base address range (AD[15:0]) for the
+ * device 12 I/O range. When this field is combined with IMASK_DEV12
+ * field, an I/O range is defined starting from the base address
+ * register value to the size defined by the mask register.
+ */
+ // Set device 12 I/O range at 0xe404-0xe405 and enable.
+ DEVRESE + 0, 0x00, 0x04,
+ DEVRESE + 1, 0x00, 0xe4,
+ DEVRESE + 2, 0x00, 0x11,
+};
+
+static void pwrmgt_init(struct device *dev)
+{
+ /* Sets the base address of power management ports. */
+ pci_write_config16(dev, PMBA, PM_IO_BASE | 1);
+
+ u8 val = pci_read_config8(dev, PMREGMISC);
+ pci_write_config8(dev, PMREGMISC, val | 1);
+
+ int i;
+ for (i = 0; i < 64; i++) {
+ if ((i != 14) || (i != 15))
+// printk("REG %02x is %02x\n", inb(PM_IO_BASE + i));
+ printk(BIOS_INFO, "REG %02x is %02x\n", i, inb(PM_IO_BASE + i));
+ }
+
+ outl(0x00200004, PM_IO_BASE + 0x28);
+
+ /* Clear status events. */
+ outw(0xffff, PM_IO_BASE + 0x00);
+ outw(0xffff, PM_IO_BASE + 0xC);
+ outw(0xffff, PM_IO_BASE + 0x18);
+
+ for (i = 0; i < 64; i++) {
+ if ((i != 14) || (i != 15))
+// printk("REG %02x is %02x\n", inb(PM_IO_BASE + i));
+ printk(BIOS_INFO, "REG %02x is %02x\n", i, inb(PM_IO_BASE + i));
+ }
+}
+
static const struct smbus_bus_operations lops_smbus_bus = {
};
@@ -34,7 +95,7 @@
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = 0,
+ .init = pwrmgt_init,
.scan_bus = scan_static_bus,
.enable = 0,
.ops_pci = 0, /* No subsystem IDs on 82371EB! */
===================================================================
@@ -1,14 +1,15 @@
#include <device/smbus_def.h>
-#define SMBHST_STATUS 0x0
-#define SMBHST_CTL 0x2
-#define SMBHST_CMD 0x3
-#define SMBHST_ADDR 0x4
-#define SMBHST_DAT 0x5
+#define SMBUS_IO_BASE 0x0f00
+#define SMBHST_STATUS 0x0
+#define SMBHST_CTL 0x2
+#define SMBHST_CMD 0x3
+#define SMBHST_ADDR 0x4
+#define SMBHST_DAT 0x5
-#define SMBUS_TIMEOUT (100*1000*10)
-#define SMBUS_STATUS_MASK 0x1e
-#define SMBUS_ERROR_FLAG (1<<2)
+#define SMBUS_TIMEOUT (100 * 1000 * 10)
+#define SMBUS_STATUS_MASK 0x1e
+#define SMBUS_ERROR_FLAG (1 << 2)
void enable_smbus(void);
int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address);
@@ -41,7 +42,7 @@
}
#endif
} while(--loops);
- return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+ return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
static int smbus_wait_until_done(unsigned smbus_io_base)
@@ -63,7 +64,7 @@
break;
}
} while(--loops);
- return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+ return loops ? 0 : SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
@@ -90,7 +91,7 @@
outb(0, smbus_io_base + SMBHST_DAT);
/* start a byte read with interrupts disabled */
- outb( (0x02 << 2)|(1<<6), smbus_io_base + SMBHST_CTL);
+ outb( (0x02 << 2)|(1 << 6), smbus_io_base + SMBHST_CTL);
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
===================================================================
@@ -30,6 +30,8 @@
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
#elif defined(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)
#include "../../../southbridge/intel/i82801dx/i82801dx.h"
+#elif defined(CONFIG_SOUTHBRIDGE_INTEL_I82371EB)
+#include "../../../southbridge/intel/i82371eb/i82371eb.h"
#else
#error "Southbridge needs SMM handler support."
#endif
===================================================================
@@ -0,0 +1,165 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Based on src/southbridge/via/vt8237r/vt8237_fadt.c */
+
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <device/pci.h>
+/* PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI */
+#include <device/pci_ids.h>
+//#include "i82371eb.h" /* PM_IO_BASE, PMCNTRL */
+#include "southbridge/intel/i82371eb/i82371eb.h" /* PM_IO_BASE, PMCNTRL */
+
+/**
+ * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
+ */
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ device_t dev;
+
+ /* Power management controller */
+ dev = dev_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); /* pci_ids.h */
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = 244;
+ header->revision = 1;
+ memcpy(header->oem_id, "COREBO", 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 42;
+
+// fadt->firmware_ctrl = (u32)facs;
+ fadt->dsdt = (u32)dsdt;
+ fadt->preferred_pm_profile = 0;
+ fadt->sci_int = 9;
+ fadt->smi_cmd = 0xb2; // smi command port ?
+ fadt->acpi_enable = 0xa1;
+ fadt->acpi_disable = 0xa0;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0x0;
+
+ fadt->pm1a_evt_blk = PM_IO_BASE; /* PM_IO_BASE = 0xe400 */
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = PM_IO_BASE + PMCNTRL; /* PMCNTRL = 0x4 */
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = 0x0;
+ fadt->pm_tmr_blk = PM_IO_BASE + PMTMR; /* PMTMR = 0x8 */
+ fadt->gpe0_blk = PM_IO_BASE + GPSTS; /* GPSTS = 0xc */
+ fadt->gpe1_blk = 0x0;
+ fadt->gpe1_base = 0;
+ fadt->gpe1_blk_len = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 0;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 4;
+
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 0x5a;
+ fadt->p_lvl3_lat = 0x0384;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0x0d;
+ fadt->mon_alrm = 0x0;
+ fadt->century = 0x0;
+ fadt->iapc_boot_arch = 0x0;
+ fadt->flags = 0xa5;
+
+ fadt->reset_reg.space_id = 0;
+ fadt->reset_reg.bit_width = 0;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0x0;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 0;
+ fadt->x_firmware_ctl_l = (u32)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (u32)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
+}
===================================================================
@@ -2,6 +2,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -28,6 +29,11 @@
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
+# select GENERATE_ACPI_TABLES
+ select HAVE_ACPI_TABLES
+# select HAVE_ACPI_RESUME
+ select BOARD_HAS_FADT
+ select HAVE_SMI_HANDLER
config MAINBOARD_DIR
string
===================================================================
@@ -50,10 +50,10 @@
register "ide1_enable" = "1"
register "ide_legacy_enable" = "1"
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
- register "ide0_drive0_udma33_enable" = "0"
- register "ide0_drive1_udma33_enable" = "0"
- register "ide1_drive0_udma33_enable" = "0"
- register "ide1_drive1_udma33_enable" = "0"
+ register "ide0_drive0_udma33_enable" = "1"
+ register "ide0_drive1_udma33_enable" = "1"
+ register "ide1_drive0_udma33_enable" = "1"
+ register "ide1_drive1_udma33_enable" = "1"
end
end
end
===================================================================
@@ -27,6 +27,7 @@
#include <stdlib.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb.h"
+//#include "southbridge/intel/i82371eb/i82371eb_smbus.h"
#include "northbridge/intel/i440bx/raminit.h"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
@@ -37,10 +38,12 @@
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
void enable_smbus(void);
+//int do_smbus_read_byte(u8 device, u8 address);
int smbus_read_byte(u8 device, u8 address);
int spd_read_byte(unsigned int device, unsigned int address)
{
+// return do_smbus_read_byte(device, address);
return smbus_read_byte(device, address);
}
===================================================================
@@ -0,0 +1,10 @@
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+
+int mainboard_io_trap_handler(int smif)
+{
+ // Not implemented
+ return 0;
+}
===================================================================
@@ -0,0 +1 @@
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
===================================================================
@@ -0,0 +1,151 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Written by Stefan Reinauer <stepan@openbios.org>.
+ * ACPI FADT, FACS, and DSDT table support added by
+ *
+ * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
+ * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Based on src/mainboard/asus/a8v-e_se/acpi_tables.c */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h> // added
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h> // added
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/lapic.h> // added
+#include "southbridge/intel/i82371eb/i82371eb.h" // necessary ?
+
+extern const unsigned char AmlCode[];
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+/*
+ device_t dev;
+
+ dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); // pci_ids.h
+ if (!dev)
+ return current;
+*/
+ return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Create all subtables for processors. */
+// current = acpi_create_madt_lapics(current);
+
+ /* IRQ9 ACPI active low. */
+// current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+// current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+// return current;
+ // no smp on this board:
+ return 0;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_srat_t *srat;
+ acpi_rsdt_t *rsdt;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+
+ /* Align ACPI tables to 16 byte. */
+ start = (start + 0x0f) & -0x10;
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT table. */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* Clear all table memory. */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /* We explicitly add these tables later on: */
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ dsdt = (acpi_header_t *)current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ dsdt->checksum = 0; /* Don't trust iasl to get this right. */
+ dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /* If we want to use HPET timers Linux wants it in MADT. */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ acpi_add_table(rsdp, mcfg);
+
+ printk(BIOS_DEBUG, "ACPI: * SRAT\n");
+ srat = (acpi_srat_t *) current;
+ acpi_create_srat(srat);
+ current += srat->header.length;
+ acpi_add_table(rsdp, srat);
+
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
===================================================================
@@ -0,0 +1,442 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2010 Idwer Vollering <vidwer@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Based on dsdt.asl from src/mainboard/asus/a8v-e_se */
+
+/*
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
+{
+ /* Define the main processor.*/
+ Scope (\_PR)
+ {
+ Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
+ Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
+ }
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * Any others would involve declaring the wake up methods.
+ */
+
+ /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */
+ /*
+ 000b / 0x0: soft off/suspend to disk (soff/std) s5
+ 001b / 0x1: suspend to ram (str) s3
+ 010b / 0x2: powered on suspend, context lost (poscl) s1
+ 011b / 0x3: powered on suspend, cpu context lost (posccl) s2
+ 100b / 0x4: powered on suspend, context maintained (pos) s4
+ 101b / 0x5: working (clock control) s0
+ 110b / 0x6: reserved
+ 111b / 0x7: reserved
+ */
+ Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })
+ Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 })
+
+ OperationRegion (ARBI, SystemIO, 0x22, 0x1)
+
+ Field (ARBI, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x00),
+ ARDI, 1,
+ }
+
+ Method (_GTS, 1, NotSerialized)
+ {
+ If (LEqual (Arg0, 0x05))
+ {
+ Store (0x1, ARDI)
+ Sleep (0x10)
+ }
+ }
+
+ /* Root of the bus hierarchy */
+ Scope (\_SB)
+ {
+ /* Top PCI device */
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x00)
+
+ /* PCI Routing Table */
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0001FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package (0x04) { 0x0001FFFF, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package (0x04) { 0x0001FFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package (0x04) { 0x0001FFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+ Package (0x04) { 0x0004FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package (0x04) { 0x0004FFFF, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package (0x04) { 0x0004FFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package (0x04) { 0x0004FFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+ Package (0x04) { 0x0009FFFF, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package (0x04) { 0x0009FFFF, 1, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package (0x04) { 0x0009FFFF, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package (0x04) { 0x0009FFFF, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+
+ Package (0x04) { 0x000AFFFF, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package (0x04) { 0x000AFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package (0x04) { 0x000AFFFF, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package (0x04) { 0x000AFFFF, 3, \_SB.PCI0.LPCB.LNKB, 0 },
+
+ Package (0x04) { 0x000BFFFF, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package (0x04) { 0x000BFFFF, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package (0x04) { 0x000BFFFF, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package (0x04) { 0x000BFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+
+ Package (0x04) { 0x000CFFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package (0x04) { 0x000CFFFF, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package (0x04) { 0x000CFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package (0x04) { 0x000CFFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+ })
+
+ // Intel LPC Bus Device - 0:7.0
+
+ Device (LPCB)
+ {
+ Name(_ADR, 0x0040000)
+
+ OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+ Field (LPC0, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x40),
+ PMBS, 16, // PMBASE
+ Offset (0x60), // Interrupt Routing Registers
+ PRTA, 8,
+ PRTB, 8,
+ PRTC, 8,
+ PRTD, 8,
+ }
+
+ // this should go to some other file maybe
+
+ Device (LNKA)
+ {
+ Name (_HID, EISAID("PNP0C0F"))
+ Name (_UID, 1)
+
+ // Disable method
+ Method (_DIS, 0, Serialized)
+ {
+ Store (0x80, PRTA)
+ }
+
+ // Possible Resource Settings for this Link
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared)
+ { 9 }
+ //{ 10 }
+ })
+
+ // Current Resource Settings for this link
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RTLA, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLA, 1, IRQ0)
+
+ // Clear the WordField
+ Store (Zero, IRQ0)
+
+ // Set the bit from PRTA
+ ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+ Return (RTLA)
+ }
+
+ // Set Resource Setting for this IRQ link
+ Method (_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ // Which bit is set?
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTA)
+ }
+
+ // Status
+ Method (_STA, 0, Serialized)
+ {
+ If(And(PRTA, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xb)
+ }
+ }
+ } // LNKA
+
+ Device (LNKB)
+ {
+ Name (_HID, EISAID("PNP0C0F"))
+ Name (_UID, 2)
+
+ // Disable method
+ Method (_DIS, 0, Serialized)
+ {
+ Store (0x80, PRTB)
+ }
+
+ // Possible Resource Settings for this Link
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared)
+ { 9 }
+ //{ 11 }
+ })
+
+ // Current Resource Settings for this link
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RTLB, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLB, 1, IRQ0)
+
+ // Clear the WordField
+ Store (Zero, IRQ0)
+
+ // Set the bit from PRTB
+ ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+ Return (RTLB)
+ }
+
+ // Set Resource Setting for this IRQ link
+ Method (_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ // Which bit is set?
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTB)
+ }
+
+ // Status
+ Method (_STA, 0, Serialized)
+ {
+ If(And(PRTB, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xb)
+ }
+ }
+ } // LNKB
+
+ Device (LNKC)
+ {
+ Name (_HID, EISAID("PNP0C0F"))
+ Name (_UID, 3)
+
+ // Disable method
+ Method (_DIS, 0, Serialized)
+ {
+ Store (0x80, PRTC)
+ }
+
+ // Possible Resource Settings for this Link
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared)
+ { 9 }
+ //{ 10 }
+ })
+
+ // Current Resource Settings for this link
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RTLC, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLC, 1, IRQ0)
+
+ // Clear the WordField
+ Store (Zero, IRQ0)
+
+ // Set the bit from PRTC
+ ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+ Return (RTLC)
+ }
+
+ // Set Resource Setting for this IRQ link
+ Method (_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ // Which bit is set?
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTC)
+ }
+
+ // Status
+ Method (_STA, 0, Serialized)
+ {
+ If(And(PRTC, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xb)
+ }
+ }
+ } // LNKC
+
+ Device (LNKD)
+ {
+ Name (_HID, EISAID("PNP0C0F"))
+ Name (_UID, 4)
+
+ // Disable method
+ Method (_DIS, 0, Serialized)
+ {
+ Store (0x80, PRTD)
+ }
+
+ // Possible Resource Settings for this Link
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared)
+ { 9 }
+ //{ 11 }
+ })
+
+ // Current Resource Settings for this link
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RTLD, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLD, 1, IRQ0)
+
+ // Clear the WordField
+ Store (Zero, IRQ0)
+
+ // Set the bit from PRTD
+ ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+ Return (RTLD)
+ }
+
+ // Set Resource Setting for this IRQ link
+ Method (_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ // Which bit is set?
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTD)
+ }
+
+ // Status
+ Method (_STA, 0, Serialized)
+ {
+ If(And(PRTD, 0x80)) {
+ Return (0x9)
+ } Else {
+ Return (0xb)
+ }
+ }
+ } // LNKD
+ } // LPCB
+
+ Device (ISA) {
+ Name (_ADR, 0x00110000)
+
+ /* PS/2 keyboard (seems to be important for WinXP install) */
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 floppy controller */
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () {
+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+ IRQNoFlags () {6}
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
+ })
+ Return (BUF0)
+ }
+ }
+ }
+ }
+
+ }
+}
===================================================================
@@ -0,0 +1,165 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT 0xb2
+#define CST_CONTROL 0x85
+#define PST_CONTROL 0x80
+#define ACPI_DISABLE 0x1e
+#define ACPI_ENABLE 0xe1
+#define GNVS_UPDATE 0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, "CORE ", 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = ACPI_ENABLE;
+ fadt->acpi_disable = ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = PST_CONTROL;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x20;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x28;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
+ fadt->pm2_cnt_len = 2;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = CST_CONTROL;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 85;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = 0x03;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 0;
+ fadt->reset_reg.bit_width = 0;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0x0;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 0;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
===================================================================
@@ -33,4 +33,3 @@
If your board has 4 DIMM slots, you must use select this option, in
your Kconfig file of the board. On boards with 3 DIMM slots,
do _not_ select this option.
-
===================================================================
@@ -0,0 +1,40 @@
+#include <types.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+#include <device/pci_def.h>
+#include "i440bx.h"
+
+//static void dump(u8 * addr, u32 len)
+//{
+ // Not implemented
+//}
+
+//static void mbi_call(u8 subf, banner_id_t *banner_id)
+//{
+ // Not Implemented
+//}
+
+//static void smi_interface_call(void)
+//{
+ // Not implemented
+//}
+
+//static u16 reset_err_status(void)
+//{
+ // Not implemented
+// return 0;
+//}
+
+//static void dump_err_status(u32 errsts)
+//{
+ // Not implemented
+//}
+
+//void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
+//{
+ // Not implemented
+//}
===================================================================
@@ -662,8 +662,10 @@
}
struct dimm_size {
- unsigned long side1;
- unsigned long side2;
+// unsigned long side1;
+// unsigned long side2;
+ uint32_t side1;
+ uint32_t side2;
};
static struct dimm_size spd_get_dimm_size(unsigned int device)
===================================================================
@@ -20,6 +20,7 @@
driver-y += northbridge.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += i440bx_smihandler.c
+
romstage-y += raminit.c
romstage-y += debug.c
-
===================================================================
@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
@@ -15,7 +35,10 @@
static void northbridge_init(device_t dev)
{
+ u8 reg8; // as suggested by rudolf/ruik
printk(BIOS_SPEW, "Northbridge Init\n");
+ reg8 = pci_read_config16(dev, 0x7a); // as suggested by rudolf/ruik
+ pci_write_config8(dev, 0x7a, reg8 | 0x40); // as suggested by rudolf/ruik
}
static struct device_operations northbridge_operations = {
Updated against r6119, yet unfinished. Signed-off-by: Idwer Vollering <vidwer@gmail.com>