Patchwork SB700 common FADT

login
register
about
Submitter Rudolf Marek
Date 2010-12-04 13:05:40
Message ID <4CFA3CA4.30506@assembler.cz>
Download mbox | patch
Permalink /patch/2392/
State Accepted
Headers show

Comments

Rudolf Marek - 2010-12-04 13:05:40
Following patch makes just one fadt.c file.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>

svn remove src/./asus/m4a785-m/fadt.c
svn remove src/./amd/mahogany/fadt.c
svn remove src/./amd/mahogany_fam10/fadt.c
svn remove src/./amd/tilapia_fam10/fadt.c
svn remove src/./gigabyte/ma78gm/fadt.c
svn remove src/./gigabyte/ma785gmt/fadt.c
svn remove src/./jetway/pa78vm5/fadt.c
svn remove src/./asrock/939a785gmh/fadt.c
svn remove src/./iei/kino-780am2-fam10/fadt.c

I think the init of IO can be moved more early so we can use it for 
suspend/resune. As well the IO should be reserved. Maybe next patch.
Similar patch should be done for SB600. This patch is only compile tested I can 
test this on asrock next week.

Thanks,
Rudolf
Uwe Hermann - 2010-12-04 14:51:32
On Sat, Dec 04, 2010 at 02:05:40PM +0100, Rudolf Marek wrote:
> Following patch makes just one fadt.c file.
> 
> Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
> 
> svn remove src/./asus/m4a785-m/fadt.c
> svn remove src/./amd/mahogany/fadt.c
> svn remove src/./amd/mahogany_fam10/fadt.c
> svn remove src/./amd/tilapia_fam10/fadt.c
> svn remove src/./gigabyte/ma78gm/fadt.c
> svn remove src/./gigabyte/ma785gmt/fadt.c
> svn remove src/./jetway/pa78vm5/fadt.c
> svn remove src/./asrock/939a785gmh/fadt.c
> svn remove src/./iei/kino-780am2-fam10/fadt.c

Yup, great! These are full copies, even the MD5 sums match.
Good riddance.

Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

And yes, I think we should do the same on a bunch of other chipsets
indeed.

 
Uwe.
Rudolf Marek - 2010-12-11 22:26:36
Committed revision 6165.
Rudolf

Patch

Index: coreboot/src/mainboard/asrock/939a785gmh/Kconfig
===================================================================
--- coreboot.orig/src/mainboard/asrock/939a785gmh/Kconfig	2010-12-04 11:33:41.000000000 +0100
+++ coreboot/src/mainboard/asrock/939a785gmh/Kconfig	2010-12-04 11:33:47.000000000 +0100
@@ -10,7 +10,6 @@ 
 	select SOUTHBRIDGE_AMD_RS780
 	select SOUTHBRIDGE_AMD_SB700
 	select SUPERIO_WINBOND_W83627DHG
-	select BOARD_HAS_FADT
 	select HAVE_ACPI_TABLES
 	select HAVE_MP_TABLE
 	select HAVE_PIRQ_TABLE
Index: coreboot/src/mainboard/asrock/939a785gmh/acpi_tables.c
===================================================================
--- coreboot.orig/src/mainboard/asrock/939a785gmh/acpi_tables.c	2010-12-04 11:34:28.000000000 +0100
+++ coreboot/src/mainboard/asrock/939a785gmh/acpi_tables.c	2010-12-04 11:41:29.000000000 +0100
@@ -29,8 +29,7 @@ 
 #include "northbridge/amd/amdk8/amdk8_acpi.h"
 #include <arch/cpu.h>
 #include <cpu/amd/model_fxx_powernow.h>
-
-extern u16 pm_base;
+#include <southbridge/amd/sb700/sb700.h>
 
 #define DUMP_ACPI_TABLES 0
 
@@ -100,7 +99,7 @@ 
 
 unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) {
 	k8acpi_write_vars();
-	amd_model_fxx_generate_powernow(pm_base + 8, 6, 1);
+	amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1);
 	return (unsigned long) (acpigen_get_current());
 }
 
Index: coreboot/src/southbridge/amd/sb700/Makefile.inc
===================================================================
--- coreboot.orig/src/southbridge/amd/sb700/Makefile.inc	2010-12-04 11:29:37.000000000 +0100
+++ coreboot/src/southbridge/amd/sb700/Makefile.inc	2010-12-04 11:32:49.000000000 +0100
@@ -6,5 +6,7 @@ 
 driver-y += sb700_sata.c
 driver-y += sb700_hda.c
 driver-y += sb700_pci.c
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sb700_fadt.c
 ramstage-y += sb700_reset.c
 romstage-y += sb700_enable_usbdebug.c
+
Index: coreboot/src/southbridge/amd/sb700/sb700.h
===================================================================
--- coreboot.orig/src/southbridge/amd/sb700/sb700.h	2010-12-04 11:35:21.000000000 +0100
+++ coreboot/src/southbridge/amd/sb700/sb700.h	2010-12-04 11:35:58.000000000 +0100
@@ -29,6 +29,15 @@ 
 #define PM2_INDEX	0xcd0
 #define PM2_DATA	0xcd1
 
+#define SB700_ACPI_IO_BASE 0x800
+
+#define ACPI_PM_EVT_BLK		(SB700_ACPI_IO_BASE + 0x00) /* 4 bytes */
+#define ACPI_PM1_CNT_BLK	(SB700_ACPI_IO_BASE + 0x04) /* 2 bytes */
+#define ACPI_PMA_CNT_BLK	(SB700_ACPI_IO_BASE + 0x0F) /* 1 byte */
+#define ACPI_PM_TMR_BLK		(SB700_ACPI_IO_BASE + 0x18) /* 4 bytes */
+#define ACPI_GPE0_BLK		(SB700_ACPI_IO_BASE + 0x10) /* 8 bytes */
+#define ACPI_CPU_CONTROL	(SB700_ACPI_IO_BASE + 0x08) /* 6 bytes */
+
 extern void pm_iowrite(u8 reg, u8 value);
 extern u8 pm_ioread(u8 reg);
 extern void pm2_iowrite(u8 reg, u8 value);
Index: coreboot/src/southbridge/amd/sb700/sb700_fadt.c
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ coreboot/src/southbridge/amd/sb700/sb700_fadt.c	2010-12-04 11:42:41.000000000 +0100
@@ -0,0 +1,187 @@ 
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include "sb700.h"
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", SB700_ACPI_IO_BASE);
+
+	/* Prepare the header */
+	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (u32) facs;
+	fadt->dsdt = (u32) dsdt;
+	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	fadt->preferred_pm_profile = 0x03;
+	fadt->sci_int = 9;
+	/* disable system management mode by setting to 0: */
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0xf0;
+	fadt->acpi_disable = 0xf1;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0xe2;
+
+	pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
+	pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
+	pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
+	pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
+	pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
+	pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
+	pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
+	pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
+
+	/* CpuControl is in \_PR.CPU0, 6 bytes */
+	pm_iowrite(0x26, ACPI_CPU_CONTROL & 0xFF);
+	pm_iowrite(0x27, ACPI_CPU_CONTROL >> 8);
+
+	pm_iowrite(0x2A, 0);	/* AcpiSmiCmdLo */
+	pm_iowrite(0x2B, 0);	/* AcpiSmiCmdHi */
+
+	pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
+	pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
+
+	pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
+					* the contents of the PM registers at
+					* index 20-2B to decode ACPI I/O address.
+					* AcpiSmiEn & SmiCmdEn*/
+	pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
+
+	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+	fadt->pm1b_evt_blk = 0x0000;
+	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+	fadt->pm1b_cnt_blk = 0x0000;
+	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
+	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+	fadt->gpe0_blk = ACPI_GPE0_BLK;
+	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+
+	fadt->cst_cnt = 0xe3;
+	fadt->p_lvl2_lat = 101;
+	fadt->p_lvl3_lat = 1001;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0;	/* 0x7d these have to be */
+	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
+	fadt->century = 0;	/* 0x7f to make rtc alrm work */
+	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
+	fadt->flags = 0x0001c1a5;/* 0x25; */
+
+	fadt->res2 = 0;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (u32) facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32) dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 32;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+}
Index: coreboot/src/mainboard/amd/mahogany/Kconfig
===================================================================
--- coreboot.orig/src/mainboard/amd/mahogany/Kconfig	2010-12-04 13:20:06.000000000 +0100
+++ coreboot/src/mainboard/amd/mahogany/Kconfig	2010-12-04 13:26:36.000000000 +0100
@@ -10,7 +10,6 @@ 
 	select SOUTHBRIDGE_AMD_RS780
 	select SOUTHBRIDGE_AMD_SB700
 	select SUPERIO_ITE_IT8718F
-	select BOARD_HAS_FADT
 	select HAVE_ACPI_TABLES
 	select HAVE_MP_TABLE
 	select HAVE_PIRQ_TABLE
Index: coreboot/src/mainboard/amd/mahogany/acpi_tables.c
===================================================================
--- coreboot.orig/src/mainboard/amd/mahogany/acpi_tables.c	2010-12-04 13:20:06.000000000 +0100
+++ coreboot/src/mainboard/amd/mahogany/acpi_tables.c	2010-12-04 13:20:06.000000000 +0100
@@ -29,8 +29,7 @@ 
 #include "northbridge/amd/amdk8/amdk8_acpi.h"
 #include <arch/cpu.h>
 #include <cpu/amd/model_fxx_powernow.h>
-
-extern u16 pm_base;
+#include <southbridge/amd/sb700/sb700.h>
 
 #define DUMP_ACPI_TABLES 0
 
@@ -100,7 +99,7 @@ 
 
 unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) {
 	k8acpi_write_vars();
-	amd_model_fxx_generate_powernow(pm_base + 8, 6, 1);
+	amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1);
 	return (unsigned long) (acpigen_get_current());
 }
 
Index: coreboot/src/mainboard/amd/mahogany_fam10/Kconfig
===================================================================
--- coreboot.orig/src/mainboard/amd/mahogany_fam10/Kconfig	2010-12-04 13:20:06.000000000 +0100
+++ coreboot/src/mainboard/amd/mahogany_fam10/Kconfig	2010-12-04 13:27:08.000000000 +0100
@@ -10,7 +10,6 @@ 
 	select SOUTHBRIDGE_AMD_RS780
 	select SOUTHBRIDGE_AMD_SB700
 	select SUPERIO_ITE_IT8718F
-	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
Index: coreboot/src/mainboard/amd/mahogany_fam10/acpi_tables.c
===================================================================
--- coreboot.orig/src/mainboard/amd/mahogany_fam10/acpi_tables.c	2010-12-04 13:20:06.000000000 +0100
+++ coreboot/src/mainboard/amd/mahogany_fam10/acpi_tables.c	2010-12-04 13:28:01.000000000 +0100
@@ -26,7 +26,6 @@ 
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/amdfam10_sysconf.h>
-
 #include "mb_sysconf.h"
 
 #define DUMP_ACPI_TABLES 0
Index: coreboot/src/mainboard/amd/tilapia_fam10/Kconfig
===================================================================
--- coreboot.orig/src/mainboard/amd/tilapia_fam10/Kconfig	2010-12-04 13:20:07.000000000 +0100
+++ coreboot/src/mainboard/amd/tilapia_fam10/Kconfig	2010-12-04 13:28:24.000000000 +0100
@@ -10,7 +10,6 @@ 
 	select SOUTHBRIDGE_AMD_RS780
 	select SOUTHBRIDGE_AMD_SB700
 	select SUPERIO_ITE_IT8718F
-	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
Index: coreboot/src/mainboard/asus/m4a785-m/Kconfig
===================================================================
--- coreboot.orig/src/mainboard/asus/m4a785-m/Kconfig	2010-12-04 13:20:06.000000000 +0100
+++ coreboot/src/mainboard/asus/m4a785-m/Kconfig	2010-12-04 13:24:31.000000000 +0100
@@ -10,7 +10,6 @@ 
 	select SOUTHBRIDGE_AMD_SB700
 	select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
 	select SUPERIO_ITE_IT8712F
-	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
Index: coreboot/src/mainboard/gigabyte/ma785gmt/Kconfig
===================================================================
--- coreboot.orig/src/mainboard/gigabyte/ma785gmt/Kconfig	2010-12-04 13:20:07.000000000 +0100
+++ coreboot/src/mainboard/gigabyte/ma785gmt/Kconfig	2010-12-04 13:30:10.000000000 +0100
@@ -10,7 +10,6 @@ 
 	select SOUTHBRIDGE_AMD_RS780
 	select SOUTHBRIDGE_AMD_SB700
 	select SUPERIO_ITE_IT8718F
-	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
Index: coreboot/src/mainboard/gigabyte/ma78gm/Kconfig
===================================================================
--- coreboot.orig/src/mainboard/gigabyte/ma78gm/Kconfig	2010-12-04 13:20:07.000000000 +0100
+++ coreboot/src/mainboard/gigabyte/ma78gm/Kconfig	2010-12-04 13:29:28.000000000 +0100
@@ -10,7 +10,6 @@ 
 	select SOUTHBRIDGE_AMD_RS780
 	select SOUTHBRIDGE_AMD_SB700
 	select SUPERIO_ITE_IT8718F
-	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
Index: coreboot/src/mainboard/iei/kino-780am2-fam10/Kconfig
===================================================================
--- coreboot.orig/src/mainboard/iei/kino-780am2-fam10/Kconfig	2010-12-04 13:20:22.000000000 +0100
+++ coreboot/src/mainboard/iei/kino-780am2-fam10/Kconfig	2010-12-04 13:33:04.000000000 +0100
@@ -10,7 +10,6 @@ 
 	select SOUTHBRIDGE_AMD_RS780
 	select SOUTHBRIDGE_AMD_SB700
 	select SUPERIO_FINTEK_F71859
-	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
Index: coreboot/src/mainboard/jetway/pa78vm5/Kconfig
===================================================================
--- coreboot.orig/src/mainboard/jetway/pa78vm5/Kconfig	2010-12-04 13:20:07.000000000 +0100
+++ coreboot/src/mainboard/jetway/pa78vm5/Kconfig	2010-12-04 13:31:11.000000000 +0100
@@ -10,7 +10,6 @@ 
 	select SOUTHBRIDGE_AMD_RS780
 	select SOUTHBRIDGE_AMD_SB700
 	select SUPERIO_FINTEK_F71863FG
-	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE