Patchwork report OPCODE 0x03 failed (both read and write) on Zotac H55-itx A-E

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Submitter Joshua Roys
Date 2010-12-08 23:05:24
Message ID <4D000F34.8090203@gmail.com>
Download mbox | patch
Permalink /patch/2408/
State Not Applicable
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Comments

Joshua Roys - 2010-12-08 23:05:24
On 12/08/2010 05:04 AM, Felix Engemann wrote:
> 0x04: 0x6008 (HSFS)
> FLOCKDN 0, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0
> 0x50: 0x00000a0b (FRAP)
> BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b
> 0x54: 0x00000000 (FREG0: Flash Descriptor)
> 0x00000000-0x00000fff is read-only
> 0x58: 0x03ff0300 (FREG1: BIOS)
> 0x00300000-0x003fffff is read-write
> 0x5C: 0x02ff0003 (FREG2: Management Engine)
> 0x00003000-0x002fffff is locked
> 0x60: 0x00020001 (FREG3: Gigabit Ethernet)
> 0x00001000-0x00002fff is read-write
> 0x64: 0x00000fff (FREG4: Platform Data)
> 0x00fff000-0x00000fff is locked

> Reading flash... Transaction error!
> run OPCODE 0x03 failed
> Read operation failed!

Hello,

This is due to the FREGx and FRAP flash-region access and permission
registers above.  Since your BIOS doesn't lock these registers, I've
attached a patch that will modify FRAP to allow reads and writes.
Please note that there may be other things that will prevent reads or
writes from working.  Either way, please reply with another `flashrom
-V' (or -Vr, -Vw, ...).

Thanks,

Josh

Patch

diff --git a/ichspi.c b/ichspi.c
index a087a0b..7334db7 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -46,6 +46,8 @@ 
 #define ICH9_REG_FADDR         0x08	/* 32 Bits */
 #define ICH9_REG_FDATA0                0x10	/* 64 Bytes */
 
+#define ICH9_REG_FRAP          0x50	/* 32 bits */
+
 #define ICH9_REG_SSFS          0x90	/* 08 Bits */
 #define SSFS_SCIP		0x00000001
 #define SSFS_CDS		0x00000004
@@ -966,7 +968,7 @@  static void do_ich9_spi_frap(uint32_t frap, int i)
 
 	base  = ICH_FREG_BASE(freg);
 	limit = ICH_FREG_LIMIT(freg);
-	if (base == 0x1fff && limit == 0) {
+	if ((base == 0xfff || base == 0x1fff) && limit == 0) {
 		/* this FREG is disabled */
 		msg_pdbg("%s region is unused.\n", region_names[i]);
 		return;
@@ -1060,6 +1062,10 @@  int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 		msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1);
 		msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1);
 		msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1);
+		if (tmp2 & (1 << 15)) {
+			msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
+			ichspi_lock = 1;
+		}
 
 		tmp = mmio_readl(ich_spibar + 0x50);
 		msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
@@ -1072,6 +1078,12 @@  int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 		for(i = 0; i < 5; i++)
 			do_ich9_spi_frap(tmp, i);
 
+		if ((tmp & 0x1f1f) != 0x1f1f && ichspi_lock == 0) {
+			msg_pdbg("Enabling full access to all Flash Regions...  ");
+			REGWRITE32(ICH9_REG_FRAP, tmp | 0x1f1f);
+			msg_pdbg((REGREAD32(ICH9_REG_FRAP) & 0x1f1f) == 0x1f1f ? "OK\n" : "failed!\n");
+		}
+
 		msg_pdbg("0x74: 0x%08x (PR0)\n",
 			     mmio_readl(ich_spibar + 0x74));
 		msg_pdbg("0x78: 0x%08x (PR1)\n",
@@ -1097,10 +1109,6 @@  int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 			     ichspi_bbar);
 		msg_pdbg("0xB0: 0x%08x (FDOC)\n",
 			     mmio_readl(ich_spibar + 0xB0));
-		if (tmp2 & (1 << 15)) {
-			msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
-			ichspi_lock = 1;
-		}
 		ich_init_opcodes();
 		break;
 	default: