Patchwork mcp55_fadt patch to fix Microsoft Windows BSOD 0x000000A5 (0x00000011, 0x00000006 ....)

Hi,

 

The attached patch fixes a problem preventing Windows XP / 7 from booting
with bug check error A5 (0x00000011, 0x00000006) on the Gigabyte GA-M57SLI-
S4 board. Microsoft documentation states that this bug check occurs because,
"SCI_EN never becomes set in PM1 Control Register". This patch sets the
SCI_EN bit. The patch applies to any board featuring the MCP55 south bridge.

 

Signed-off-by: David Robinson <drobinson@bluechiptechnology.co.uk>

 

 


Blue Chip Technology Limited. Chowley Oak Lane, Tattenhall, Chester, Cheshire CH3 9EX Tel: 01829 772000 Registered in England 3110403 Vat No: GB 618 374134

* David Robinson <drobinson@bluechiptechnology.co.uk> [101209 10:40]:
> Hi,
> 
>  
> 
> The attached patch fixes a problem preventing Windows XP / 7 from booting with
> bug check error A5 (0x00000011, 0x00000006) on the Gigabyte GA-M57SLI- S4
> board. Microsoft documentation states that this bug check occurs because,
> “SCI_EN never becomes set in PM1 Control Register”. This patch sets the SCI_EN
> bit. The patch applies to any board featuring the MCP55 south bridge.

Wouldn't the right way to fix this be to actually implement the
acpi_enable/acpi_disable commands on smi_cmd?

Stefan

> Wouldn't the right way to fix this be to actually implement the
> acpi_enable/acpi_disable commands on smi_cmd?

No, you can put system in ACPI mode yourself. The only disadvantage is that you 
don't get poweroff if power button is pressed for less than 4 seconds (unless 
implementing IRQ9).

I think all other chipsets in coreboot are doing it this way except Intel ;)

Rudolf

Hi Stefan,

I agree that your suggestion would be the right implementation to support ACPI / Legacy systems. 

I chose this implementation due to a combination of: 
	* The mcp55 code sets the smi_cmd  to 0, disabling SMM.
	* Other main boards in the coreboot source tree seem to implement the same fix.
	* I don't have datasheets for the mcp55.

An alternative to patching this change into the coreboot source tree, could be to add an FAQ to the ACPI section of the coreboot website?

David Robinson

-----Original Message-----
From: Stefan Reinauer [mailto:stepan@coreboot.org] 
Sent: 09 December 2010 22:55
To: David Robinson
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] mcp55_fadt patch to fix Microsoft Windows BSOD 0x000000A5 (0x00000011, 0x00000006 ....)

* David Robinson <drobinson@bluechiptechnology.co.uk> [101209 10:40]:
> Hi,
> 
>  
> 
> The attached patch fixes a problem preventing Windows XP / 7 from booting with
> bug check error A5 (0x00000011, 0x00000006) on the Gigabyte GA-M57SLI- S4
> board. Microsoft documentation states that this bug check occurs because,
> “SCI_EN never becomes set in PM1 Control Register”. This patch sets the SCI_EN
> bit. The patch applies to any board featuring the MCP55 south bridge.

Wouldn't the right way to fix this be to actually implement the
acpi_enable/acpi_disable commands on smi_cmd?

Stefan


Blue Chip Technology Limited. Chowley Oak Lane, Tattenhall, Chester, Cheshire CH3 9EX Tel: 01829 772000 Registered in England 3110403 Vat No: GB 618 374134

Am 10.12.2010 08:59, schrieb Rudolf Marek:
>> Wouldn't the right way to fix this be to actually implement the
>> acpi_enable/acpi_disable commands on smi_cmd?
> 
> No, you can put system in ACPI mode yourself. The only disadvantage is
> that you don't get poweroff if power button is pressed for less than 4
> seconds (unless implementing IRQ9).
> 
> I think all other chipsets in coreboot are doing it this way except
> Intel ;)
I'd accept this in the context of this patch if fixing this for all
chipsets is put on the Infrastructure_Projects list (so it's not forgotten).

Subpar chipset support shouldn't be a long-term design goal.


Patrick

* Rudolf Marek <r.marek@assembler.cz> [101210 08:59]:
> >Wouldn't the right way to fix this be to actually implement the
> >acpi_enable/acpi_disable commands on smi_cmd?
> 
> No, you can put system in ACPI mode yourself. The only disadvantage
> is that you don't get poweroff if power button is pressed for less
> than 4 seconds (unless implementing IRQ9).
> 
> I think all other chipsets in coreboot are doing it this way except Intel ;)

Wow, so the Intel chipsets are the only ones not broken in coreboot? ;-)

Nevermind, I think this should go in but with a big warning in the code
stating that it should be released once we have a decent SMM handler for
that system.

Stefan