From patchwork Sat Dec 11 23:49:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: let high memory size be decided in cbmem.h Date: Sat, 11 Dec 2010 23:49:36 -0000 From: Rudolf Marek X-Patchwork-Id: 2419 Message-Id: <4D040E10.1080507@assembler.cz> To: coreboot@coreboot.org Attaching refreshed patch. Should be same as previously posted. Thanks, Rudolf Acked-by: Peter Stuge Index: coreboot/src/include/cbmem.h =================================================================== --- coreboot.orig/src/include/cbmem.h 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/include/cbmem.h 2010-12-12 00:04:47.000000000 +0100 @@ -21,13 +21,14 @@ #define _CBMEM_H_ /* Reserve 64k for ACPI and other tables */ -#define HIGH_MEMORY_TABLES ( 64 * 1024 ) +#define HIGH_MEMORY_DEF_SIZE ( 64 * 1024 ) +extern uint64_t high_tables_base, high_tables_size; #if CONFIG_HAVE_ACPI_RESUME -#define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_TABLES) -#define HIGH_MEMORY_SAVE ( HIGH_MEMORY_SIZE - HIGH_MEMORY_TABLES ) +#define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE) +#define HIGH_MEMORY_SAVE ( HIGH_MEMORY_SIZE - HIGH_MEMORY_DEF_SIZE ) #else -#define HIGH_MEMORY_SIZE HIGH_MEMORY_TABLES +#define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE #endif #define CBMEM_ID_FREESPACE 0x46524545 Index: coreboot/src/mainboard/emulation/qemu-x86/northbridge.c =================================================================== --- coreboot.orig/src/mainboard/emulation/qemu-x86/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/mainboard/emulation/qemu-x86/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -11,8 +11,7 @@ #include #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif #define CMOS_ADDR_PORT 0x70 @@ -49,8 +48,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif assign_resources(dev->link_list); Index: coreboot/src/northbridge/amd/amdfam10/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/amd/amdfam10/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/amd/amdfam10/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -841,8 +841,7 @@ #endif #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif #if CONFIG_GFXUMA == 1 @@ -1033,13 +1032,13 @@ if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, - high_tables_base); + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", + HIGH_MEMORY_SIZE / 1024, high_tables_base); } #endif } @@ -1078,11 +1077,11 @@ if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_size = HIGH_MEMORY_SIZE; } #endif } Index: coreboot/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/amd/amdk8/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/amd/amdk8/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -820,8 +820,6 @@ #if CONFIG_WRITE_HIGH_TABLES==1 #include -#define HIGH_TABLES_SIZE ((HIGH_MEMORY_SIZE + 1024) / 1024) -extern uint64_t high_tables_base, high_tables_size; #endif #if CONFIG_GFXUMA == 1 @@ -1020,13 +1018,13 @@ if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, - high_tables_base); + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", + HIGH_MEMORY_SIZE / 1024, high_tables_base); } #endif } @@ -1065,11 +1063,11 @@ if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_size = HIGH_MEMORY_SIZE; } #endif } Index: coreboot/src/northbridge/amd/gx1/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/amd/gx1/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/amd/gx1/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -67,8 +67,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) @@ -116,8 +115,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif /* Report the memory regions */ Index: coreboot/src/northbridge/amd/gx2/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/amd/gx2/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/amd/gx2/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -432,8 +432,7 @@ void chipsetInit (void); #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void enable_dev(struct device *dev) @@ -457,8 +456,8 @@ tomk = ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE; #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif ram_resource(dev, 0, 0, tomk); } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { Index: coreboot/src/northbridge/amd/lx/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/amd/lx/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/amd/lx/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -373,8 +373,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) @@ -396,8 +395,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } Index: coreboot/src/northbridge/intel/e7501/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/intel/e7501/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/intel/e7501/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -10,8 +10,7 @@ #include "chip.h" #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) @@ -92,8 +91,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Index: coreboot/src/northbridge/intel/e7520/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/intel/e7520/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/intel/e7520/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -17,8 +17,7 @@ static unsigned int max_bus; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) @@ -111,8 +110,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Index: coreboot/src/northbridge/intel/e7525/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/intel/e7525/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/intel/e7525/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -17,8 +17,7 @@ static unsigned int max_bus; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) @@ -111,8 +110,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Index: coreboot/src/northbridge/intel/i3100/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/intel/i3100/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/intel/i3100/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -38,8 +38,7 @@ static u32 max_bus; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) @@ -132,8 +131,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Index: coreboot/src/northbridge/intel/i440bx/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/intel/i440bx/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/intel/i440bx/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -34,8 +34,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void i440bx_domain_set_resources(device_t dev) @@ -75,8 +74,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Index: coreboot/src/northbridge/intel/i440lx/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/intel/i440lx/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/intel/i440lx/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -63,8 +63,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void i440lx_domain_set_resources(device_t dev) @@ -104,8 +103,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Index: coreboot/src/northbridge/intel/i82810/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/intel/i82810/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/intel/i82810/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -84,8 +84,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) @@ -150,8 +149,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif assign_resources(dev->link_list); } Index: coreboot/src/northbridge/intel/i82830/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/intel/i82830/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/intel/i82830/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -65,8 +65,7 @@ } #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) { @@ -119,8 +118,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } Index: coreboot/src/northbridge/intel/i855/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/intel/i855/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/intel/i855/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -54,8 +54,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) { @@ -112,8 +111,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Index: coreboot/src/northbridge/intel/i945/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/intel/i945/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/intel/i945/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -93,8 +93,7 @@ } #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 1024 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) @@ -183,8 +182,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } Index: coreboot/src/northbridge/via/cn400/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/via/cn400/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/via/cn400/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -178,9 +178,7 @@ #endif #if CONFIG_WRITE_HIGH_TABLES==1 -/* maximum size of high tables in KB */ -#define HIGH_TABLES_SIZE 64 -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void cn400_domain_set_resources(device_t dev) @@ -211,9 +209,10 @@ #if CONFIG_WRITE_HIGH_TABLES == 1 /* Locate the High Tables at the Top of Low Memory below the Video RAM */ - high_tables_base = (uint64_t) (tolmk - (CONFIG_VIDEO_MB *1024) - HIGH_TABLES_SIZE) * 1024; - high_tables_size = (uint64_t) HIGH_TABLES_SIZE* 1024; - printk(BIOS_SPEW, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); + high_tables_base = ((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_SPEW, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", + tomk*1024, high_tables_base, high_tables_size); #endif /* Report the memory regions. */ Index: coreboot/src/northbridge/via/cn700/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/via/cn700/northbridge.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/northbridge/via/cn700/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -98,9 +98,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -/* maximum size of high tables in KB */ -#define HIGH_TABLES_SIZE 64 -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) @@ -141,9 +139,10 @@ } #if CONFIG_WRITE_HIGH_TABLES == 1 - high_tables_base = (tolmk - CONFIG_VIDEO_MB * 1024 - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); + high_tables_base = ((tolmk - CONFIG_VIDEO_MB * 1024) * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", + tomk*1024, high_tables_base, high_tables_size); #endif /* Report the memory regions. */ Index: coreboot/src/northbridge/via/cx700/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/via/cx700/northbridge.c 2010-12-12 00:04:37.000000000 +0100 +++ coreboot/src/northbridge/via/cx700/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -33,9 +33,7 @@ #include "northbridge.h" #if CONFIG_WRITE_HIGH_TABLES==1 -/* maximum size of high tables in KB */ -#define HIGH_TABLES_SIZE 64 -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) @@ -77,9 +75,10 @@ } #if CONFIG_WRITE_HIGH_TABLES == 1 - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE* 1024; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", + tomk*1024, high_tables_base, high_tables_size); #endif /* Report the memory regions */ Index: coreboot/src/northbridge/via/vt8601/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/via/vt8601/northbridge.c 2010-12-12 00:04:37.000000000 +0100 +++ coreboot/src/northbridge/via/vt8601/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -46,9 +46,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -/* maximum size of high tables in KB */ -#define HIGH_TABLES_SIZE 64 -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) @@ -92,9 +90,10 @@ } #if CONFIG_WRITE_HIGH_TABLES == 1 - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE* 1024; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", + tomk*1024, high_tables_base, high_tables_size); #endif /* Report the memory regions */ Index: coreboot/src/northbridge/via/vt8623/northbridge.c =================================================================== --- coreboot.orig/src/northbridge/via/vt8623/northbridge.c 2010-12-12 00:04:37.000000000 +0100 +++ coreboot/src/northbridge/via/vt8623/northbridge.c 2010-12-12 00:04:47.000000000 +0100 @@ -106,9 +106,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -/* maximum size of high tables in KB */ -#define HIGH_TABLES_SIZE 64 -extern uint64_t high_tables_base, high_tables_size; +#include #endif static void pci_domain_set_resources(device_t dev) @@ -152,9 +150,10 @@ } #if CONFIG_WRITE_HIGH_TABLES == 1 - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE* 1024; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", + tomk*1024, high_tables_base, high_tables_size); #endif /* Report the memory regions */ Index: coreboot/src/lib/cbmem.c =================================================================== --- coreboot.orig/src/lib/cbmem.c 2010-12-12 00:04:38.000000000 +0100 +++ coreboot/src/lib/cbmem.c 2010-12-12 00:04:47.000000000 +0100 @@ -193,7 +193,6 @@ #if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; #endif -extern uint64_t high_tables_base, high_tables_size; void cbmem_initialize(void) {