Patchwork [4/6] Geode GX2 cleanup patch

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Submitter Nils
Date 2010-12-23 00:04:30
Message ID <201012230104.30382.njacobs8@hetnet.nl>
Download mbox | patch
Permalink /patch/2448/
State Superseded
Headers show

Comments

Nils - 2010-12-23 00:04:30
Remove wrong GX2 processor IIOC mode setting on CS5535 southbridge code
and fix CIS mode comments.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>

Thanks, Nils.
Peter Stuge - 2010-12-26 05:08:36
Nils wrote:
> Remove wrong GX2 processor IIOC mode setting on CS5535 southbridge
> code and fix CIS mode comments.

Hm, please talk a little about this?


> +++ src/southbridge/amd/cs5535/early_setup.c	(working copy)
> @@ -107,15 +107,11 @@
..
> -	//Only do this if we are building for 5535
> -	msr.lo = 0x2;
> -	msr.hi = 0x0;
> -	wrmsr(VIP_GIO_MSR_SEL, msr);

This code is not added to another place by this patch. Is it simply
completely bogus, but harmless, for 5535? And harmful for GX2? Please
explain a little?


> +++ src/include/cpu/amd/gx2def.h	(working copy)
..
> +#define	FG_GIO_MSR_SEL		(MSR_FG + 0x2010)
..

> -#define VIP_GIO_MSR_SEL		(MSR_VIP + 0x2010)

(Why remove this?)


> +++ src/cpu/amd/model_gx2/cpureginit.c	(working copy)
..
> -	msrnum = MSR_FG + 0x10;
..
> +	msrnum = FG_GIO_MSR_SEL;

This is not the same MSR. Please explain? FG_GIO_MSR_SEL is defined
to MSR_FG + 0x2010 above, so this particular change changes which MSR
is being accessed. Is on purpose?


//Peter

Patch

Index: src/southbridge/amd/cs5535/early_setup.c
===================================================================
--- src/southbridge/amd/cs5535/early_setup.c	(revision 6205)
+++ src/southbridge/amd/cs5535/early_setup.c	(working copy)
@@ -107,15 +107,11 @@ 
 {
 	msr_t msr;
 
-	/* setup CPU interface serial to mode C on both sides */
+	/* Setup CPU serial SouthBridge interface to mode C. */
 	msr = rdmsr(GLPCI_SB_CTRL);
 	msr.lo &= ~0x18;
 	msr.lo |= 0x10;
 	wrmsr(GLPCI_SB_CTRL, msr);
-	//Only do this if we are building for 5535
-	msr.lo = 0x2;
-	msr.hi = 0x0;
-	wrmsr(VIP_GIO_MSR_SEL, msr);
 }
 
 static void dummy(void)
Index: src/southbridge/amd/cs5536/early_setup.c
===================================================================
--- src/southbridge/amd/cs5536/early_setup.c	(revision 6205)
+++ src/southbridge/amd/cs5536/early_setup.c	(working copy)
@@ -145,7 +145,7 @@ 
 {
 	msr_t msr;
 
-	/* setup CPU interface serial to mode B to match CPU */
+	/* Setup CPU serial SouthBridge interface to mode C. */
 	msr = rdmsr(GLPCI_SB_CTRL);
 	msr.lo &= ~0x18;
 	msr.lo |= 0x10;
Index: src/include/cpu/amd/gx2def.h
===================================================================
--- src/include/cpu/amd/gx2def.h	(revision 6205)
+++ src/include/cpu/amd/gx2def.h	(working copy)
@@ -387,13 +387,13 @@ 
 /* FooGlue GLIU1 port 5 */
 #define	FG_GLD_MSR_CAP		(MSR_FG + 0x2000)
 #define	FG_GLD_MSR_PM		(MSR_FG + 0x2004)
+#define	FG_GIO_MSR_SEL		(MSR_FG + 0x2010)
 
 /* VIP GLIU1 port 5 */
 #define VIP_GLD_MSR_CAP		(MSR_VIP + 0x2000)
 #define VIP_GLD_MSR_CONFIG	(MSR_VIP + 0x2001)
 #define VIP_GLD_MSR_PM		(MSR_VIP + 0x2004)
 #define VIP_BIST		(MSR_VIP + 0x2005)
-#define VIP_GIO_MSR_SEL		(MSR_VIP + 0x2010)
 
 /* AES GLIU1 port 6 */
 #define AES_GLD_MSR_CAP		(MSR_AES + 0x2000)
Index: src/cpu/amd/model_gx2/cpureginit.c
===================================================================
--- src/cpu/amd/model_gx2/cpureginit.c	(revision 6205)
+++ src/cpu/amd/model_gx2/cpureginit.c	(working copy)
@@ -90,16 +90,13 @@ 
 	msr.lo =  0x00000603C;
 	wrmsr(msrnum, msr);
 
-/* Only do this if we are building for 5535 */
 /* FooGlue Setup */
-#if 1
-	/* Enable CIS mode B in FooGlue */
-	msrnum = MSR_FG + 0x10;
+	/* Set CS5535/CS5536 mode in FooGlue */
+	msrnum = FG_GIO_MSR_SEL;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~3;
-	msr.lo |= 2;		/* ModeB */
+	msr.lo |= 2;		/* IIOC mode CS5535/CS5536 enable.  */
 	wrmsr(msrnum, msr);
-#endif
 
 /* Disable DOT PLL. Graphics init will enable it if needed. */
 	msrnum = GLCP_DOTPLL;