From patchwork Mon Dec 27 13:24:56 2010
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Subject: [3/6,V2] Geode GX2 cleanup patch
Date: Mon, 27 Dec 2010 13:24:56 -0000
From: Nils <njacobs8@hetnet.nl>
X-Patchwork-Id: 2457
Message-Id: <201012271424.56313.njacobs8@hetnet.nl>
To: coreboot@coreboot.org

Use die()  to assure the processor can't wake up from an interrupt.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>

This was suggested by Peter and Stefan. Thanks!
I also included the same patch for Geode LX and added a second die()
to Geode GX2 at the same place as in the LX code.

I boot tested it on my Wyse S50 and it seems to work.

Thanks, Nils.


Index: src/northbridge/amd/gx2/pll_reset.c
===================================================================
--- src/northbridge/amd/gx2/pll_reset.c	(revision 6215)
+++ src/northbridge/amd/gx2/pll_reset.c	(working copy)
@@ -78,9 +78,8 @@
 	} else if (CONFIG_GX2_PROCESSOR_MHZ == 300) {
 		DEFAULT_FBDIV = 18;
 	} else {
-		printk(BIOS_ERR, "Unsupported GX2_PROCESSOR_MHZ setting!\n");
 		post_code(POST_PLL_CPU_VER_FAIL);
-		__asm__ __volatile__("hlt\n");
+		die("Unsupported GX2_PROCESSOR_MHZ setting!\n");
 	}
 
 	/* clear the Bypass bit */
@@ -186,7 +185,7 @@
 
 		/* You should never get here..... The chip has reset. */
 		post_code(POST_PLL_RESET_FAIL);
-		while (1);
+		die("CONFIGURING PLL FAILURE\n");
 
 	} /* we haven't configured the PLL; do it now */
 
Index: src/northbridge/amd/lx/pll_reset.c
===================================================================
--- src/northbridge/amd/lx/pll_reset.c	(revision 6215)
+++ src/northbridge/amd/lx/pll_reset.c	(working copy)
@@ -59,9 +59,8 @@
 		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
 
 		/* You should never get here..... The chip has reset. */
-		printk(BIOS_ERR, "CONFIGURING PLL FAILURE\n");
 		post_code(POST_PLL_RESET_FAIL);
-		__asm__ __volatile__("hlt\n");
+		die("CONFIGURING PLL FAILURE\n");
 
 	}
 	printk(BIOS_DEBUG, "PLL configured.\n");