From patchwork Wed Dec 29 19:05:15 2010
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Subject: [4/7] Geode GX2 cleanup next round
Date: Wed, 29 Dec 2010 19:05:15 -0000
From: Nils <njacobs8@hetnet.nl>
X-Patchwork-Id: 2466
Message-Id: <201012292005.15446.njacobs8@hetnet.nl>
To: coreboot@coreboot.org

-Remove the AES register names.(GX2 has no AES registers)

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>

Thanks, Nils.


Index: src/include/cpu/amd/gx2def.h
===================================================================
--- src/include/cpu/amd/gx2def.h	(revision 6218)
+++ src/include/cpu/amd/gx2def.h	(working copy)
@@ -77,7 +77,6 @@
 #define	GL1_GLCP	3
 #define	GL1_PCI		4
 #define	GL1_FG		5
-#define GL1_AES		6
 
 #define	MSR_GLIU0	(GL0_GLIU0	<< 29) + (1 << 28)	/* 1000xxxx - To get on GeodeLink one bit has to be set */
 #define	MSR_MC		(GL0_MC		<< 29)			/* 2000xxxx */
@@ -90,10 +89,6 @@
 #define	MSR_GLCP	(GL1_GLCP << 26) + MSR_GLIU1		/* 4C00xxxx */
 #define	MSR_PCI		(GL1_PCI << 26) + MSR_GLIU1		/* 5000xxxx */
 #define	MSR_FG		(GL1_FG << 26) + MSR_GLIU1		/* 5400xxxx */
-#define MSR_AES		((GL1_AES << 26) + MSR_GLIU1)		/* 5800xxxx */
-
-/* South Bridge */
-#define SB_PORT	2			/* port of the SouthBridge */
 
 /* GeodeLink Interface Unit 0 (GLIU0) port0 */
 #define	GLIU0_GLD_MSR_CAP		(MSR_GLIU0 + 0x2000)
@@ -389,12 +384,6 @@
 #define	FG_GIO_MSR_SEL		(MSR_FG + 0x2010)
 #define	FG_BIST			(MSR_FG + 0x2005)
 
-/* AES GLIU1 port 6 */
-#define AES_GLD_MSR_CAP		(MSR_AES + 0x2000)
-#define AES_GLD_MSR_CONFIG	(MSR_AES + 0x2001)
-#define AES_GLD_MSR_PM		(MSR_AES + 0x2004)
-#define AES_CONTROL		(MSR_AES + 0x2006)
-
 /* from MC spec */
 #define MIN_MOD_BANKS		1
 #define MAX_MOD_BANKS		2
Index: src/northbridge/amd/gx2/northbridgeinit.c
===================================================================
--- src/northbridge/amd/gx2/northbridgeinit.c	(revision 6218)
+++ src/northbridge/amd/gx2/northbridgeinit.c	(working copy)
@@ -99,7 +99,6 @@
 	{GLPCI_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0027}},		/* GLPCI Priority + PID */
 	{GLCP_GLD_MSR_CONF,		{.hi=0x00,.lo=0x0001}},		/* GLCP Priority + PID */
 	{FG_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0622}},		/* FG PID */
-	{AES_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0013}},		/* AES PID */
 	{0x0FFFFFFFF, 			{0x0FFFFFFFF, 0x0FFFFFFFF}},	/* END */
 };