From patchwork Wed Dec 29 19:05:27 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [6/7] Geode GX2 cleanup next round Date: Wed, 29 Dec 2010 19:05:27 -0000 From: Nils X-Patchwork-Id: 2468 Message-Id: <201012292005.27570.njacobs8@hetnet.nl> To: coreboot@coreboot.org -Clean up GX2 northbridge code to match Geode LX code. -Add missing copyright header to northbridge.c. Signed-off-by: Nils Jacobs Thanks, Nils. Index: src/northbridge/amd/gx2/northbridge.c =================================================================== --- src/northbridge/amd/gx2/northbridge.c (revision 6218) +++ src/northbridge/amd/gx2/northbridge.c (working copy) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include #include #include @@ -9,7 +29,6 @@ #include #include "chip.h" #include "northbridge.h" -#include #include #include #include @@ -313,25 +332,26 @@ static void northbridge_init(device_t dev) { struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; - printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); + printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__); enable_shadow(dev); irq_init_steering(dev, nb->irqmap); } -/* due to vsa interactions, we need not not touch the nb settings ... */ -/* this is a test -- we are not sure it will work -- but it ought to */ -static void set_resources(struct device *dev) +static void northbridge_set_resources(struct device *dev) { + uint8_t line; + struct bus *bus; for(bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { + printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n", + bus->secondary); assign_resources(bus); } } -#if 0 /* set a default latency timer */ pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); @@ -341,18 +361,17 @@ } /* zero the irq settings */ - u8 line = pci_read_config8(dev, PCI_INTERRUPT_PIN); + line = pci_read_config8(dev, PCI_INTERRUPT_PIN); if (line) { pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); } /* set the cache line size, so far 64 bytes is good for everyone */ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); -#endif } static struct device_operations northbridge_operations = { .read_resources = pci_dev_read_resources, - .set_resources = set_resources, + .set_resources = northbridge_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .enable = 0, @@ -365,24 +384,64 @@ .device = PCI_DEVICE_ID_NS_GX2, }; -/* FIXME handle UMA correctly. */ -#define FRAMEBUFFERK 4096 +#if CONFIG_WRITE_HIGH_TABLES==1 +#include +#endif static void pci_domain_set_resources(device_t dev) { + int idx; + u32 tomk; + device_t mc_dev; + + printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); + + mc_dev = dev->link_list->children; + if (mc_dev) { + tomk = get_systop() / 1024; + /* Report the memory regions + All memory up to systop except 0xa0000-0xbffff */ + idx = 10; + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */ + +#if CONFIG_WRITE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; +#endif + } + assign_resources(dev->link_list); } +static void pci_domain_enable(device_t dev) +{ + printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); + + /* do this here for now -- this chip really breaks our device model */ + northbridge_init_early(); + cpubug(); + chipsetinit(); + setup_gx2(); + print_conf(); + do_vsmbios(); + graphics_init(); + pci_set_method(dev); +} + static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, .enable_resources = NULL, - .init = NULL, .scan_bus = pci_domain_scan_bus, + .enable = pci_domain_enable, }; static void cpu_bus_init(device_t dev) { + printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); + initialize_cpus(dev->link_list); } @@ -398,43 +457,16 @@ .scan_bus = 0, }; -void chipsetInit (void); - -#if CONFIG_WRITE_HIGH_TABLES==1 -#include -#endif - static void enable_dev(struct device *dev) { - printk(BIOS_DEBUG, "gx2 north: enable_dev\n"); - void do_vsmbios(void); + printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n", + __func__, dev->path.type); /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { - u32 tomk; - printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n"); - /* cpubug MUST be called before setup_gx2(), so we force the issue here */ - northbridgeinit(); - cpubug(); - chipsetinit(); - setup_gx2(); - print_conf(); - do_vsmbios(); - graphics_init(); + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) dev->ops = &pci_domain_ops; - pci_set_method(dev); - tomk = ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE; -#if CONFIG_WRITE_HIGH_TABLES==1 - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; -#endif - ram_resource(dev, 0, 0, tomk); - } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { - printk(BIOS_DEBUG, "DEVICE_PATH_APIC_CLUSTER\n"); + else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) dev->ops = &cpu_bus_ops; - } - printk(BIOS_DEBUG, "gx2 north: end enable_dev\n"); } struct chip_operations northbridge_amd_gx2_ops = { Index: src/northbridge/amd/gx2/northbridgeinit.c =================================================================== --- src/northbridge/amd/gx2/northbridgeinit.c (revision 6218) +++ src/northbridge/amd/gx2/northbridgeinit.c (working copy) @@ -693,8 +693,32 @@ wrmsr(CPU_RCONF_BYPASS, msr); } +uint32_t get_systop(void) +{ + struct gliutable *gl = 0; + uint32_t systop; + msr_t msr; + int i; + + for (i = 0; gliu0table[i].desc_name != GL_END; i++) { + if (gliu0table[i].desc_type == R_SYSMEM) { + gl = &gliu0table[i]; + break; + } + } + if (gl) { + msr = rdmsr(gl->desc_name); + systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8); + systop += 0x1000; /* 4K */ + } else { + systop = + ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024; + } + return systop; +} + /* Core Logic initialization: Host bridge. */ -void northbridgeinit(void) +void northbridge_init_early(void) { msr_t msr; int i; Index: src/northbridge/amd/gx2/northbridge.h =================================================================== --- src/northbridge/amd/gx2/northbridge.h (revision 6218) +++ src/northbridge/amd/gx2/northbridge.h (working copy) @@ -1,14 +1,16 @@ #ifndef NORTHBRIDGE_AMD_GX2_H #define NORTHBRIDGE_AMD_GX2_H -#if !defined(__ROMCC__) && !defined(ASSEMBLY) -#if defined(__PRE_RAM__) -#else +#include + +/* northbridge.c */ unsigned int gx2_scan_root_bus(device_t root, unsigned int max); int sizeram(void); +void do_vsmbios(void); void graphics_init(void); -void northbridgeinit(void); -#endif -#endif +/* northbridgeinit.c */ +void northbridge_init_early(void); +uint32_t get_systop(void); + #endif /* NORTHBRIDGE_AMD_GX2_H */