From patchwork Wed Dec 29 19:05:32 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [7/7] Geode GX2 cleanup next round Date: Wed, 29 Dec 2010 19:05:32 -0000 From: Nils X-Patchwork-Id: 2469 Message-Id: <201012292005.32720.njacobs8@hetnet.nl> To: coreboot@coreboot.org Move hardcoded IRQ defining from northbridge.c to irq_tables.c . Signed-off-by: Nils Jacobs Thanks, Nils. Index: src/mainboard/wyse/s50/irq_tables.c =================================================================== --- src/mainboard/wyse/s50/irq_tables.c (revision 6218) +++ src/mainboard/wyse/s50/irq_tables.c (working copy) @@ -20,6 +20,24 @@ #include +/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 5 +#define PIRQC 10 +#define PIRQD 10 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ Index: src/mainboard/wyse/s50/mainboard.c =================================================================== --- src/mainboard/wyse/s50/mainboard.c (revision 6218) +++ src/mainboard/wyse/s50/mainboard.c (working copy) @@ -21,13 +21,21 @@ #include #include -#include -#include -#include -#include #include "chip.h" +static void init(struct device *dev) +{ + printk(BIOS_DEBUG, "S50 ENTER %s\n", __func__); + printk(BIOS_DEBUG, "S50 EXIT %s\n", __func__); +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + struct chip_operations mainboard_ops = { CHIP_NAME("WYSE S50 Mainboard") + .enable_dev = enable_dev, }; Index: src/mainboard/amd/rumba/irq_tables.c =================================================================== --- src/mainboard/amd/rumba/irq_tables.c (revision 6218) +++ src/mainboard/amd/rumba/irq_tables.c (working copy) @@ -7,6 +7,24 @@ #include +/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 5 +#define PIRQC 10 +#define PIRQD 10 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ Index: src/mainboard/lippert/frontrunner/irq_tables.c =================================================================== --- src/mainboard/lippert/frontrunner/irq_tables.c (revision 6218) +++ src/mainboard/lippert/frontrunner/irq_tables.c (working copy) @@ -7,6 +7,24 @@ #include +/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 5 +#define PIRQC 10 +#define PIRQD 10 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ Index: src/northbridge/amd/gx2/northbridge.c =================================================================== --- src/northbridge/amd/gx2/northbridge.c (revision 6218) +++ src/northbridge/amd/gx2/northbridge.c (working copy) @@ -228,29 +228,6 @@ #define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE) #define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE) -/* note that dev is NOT used -- yet */ -static void irq_init_steering(struct device *dev, u16 irq_map) -{ - /* Set up IRQ steering */ - u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; - - printk(BIOS_DEBUG, "%s(%p [%08X], %04X)\n", __func__, dev, pciAddr, irq_map); - - /* The IRQ steering values (in hex) are effectively dcba, where: - * represents the IRQ for INTA, - * represents the IRQ for INTB, - * represents the IRQ for INTC, and - * represents the IRQ for INTD. - * Thus, a value of irq_map = 0xAA5B translates to: - * INTA = IRQB (IRQ 11) - * INTB = IRQ5 (IRQ 5) - * INTC = IRQA (IRQ 10) - * INTD = IRQA (IRQ 10) - */ - outl(pciAddr & ~3, 0xCF8); - outl(irq_map, 0xCFC); -} - /* setup_gx2_cache * * Returns the amount of memory (in KB) available to the system. This is the @@ -331,11 +308,9 @@ static void northbridge_init(device_t dev) { - struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__); enable_shadow(dev); - irq_init_steering(dev, nb->irqmap); } static void northbridge_set_resources(struct device *dev)